extending a signal pulse

[Johan Bernspĺng]

Hi all,

What would be the optimal way, in terms of device utilization and
functionality, to exstend the length of the time a signal is asserted
from one clock cycle to four clock cycles. I.e.
[pseduo code:]
if signal_a is asserted then
signal_b is asserted for four clk;

Is it possible to accomplish the function by utilizing an SRL16, or is
there a better solution? Or should I simply create four delayed versions
of signal_a, and OR them together to form signal_b?

I'm working with a Virtex-2 device.

regards
--
-----------------------------------------------
Please remove the x's in the email address if
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Johan Bernspĺng, xjohbex@xfoix.se

 

[A Beaujean]

There is no precise answer U can give without knowing all the aspects
of your problem.

For instance, your proposal to have an OR function may be dangerous if
you use the result directly or indirectly as a clock to some other
logic. In that case, I am pretty sure the output will glitch, which is
not a problem at all if the output signal is reclocked for further
use.

Apart from that remark, many solutions are possible, as you stated.
Just try them . Another idea is to use a two bit state machine that
controls an output flip-flop.

Johan Bernspĺng <xjohbex@xfoix.se> wrote in message news:<ccjddj$39r$1@mercur.foi.se>...

Hi all,

What would be the optimal way, in terms of device utilization and
functionality, to exstend the length of the time a signal is asserted
from one clock cycle to four clock cycles. I.e.
[pseduo code:]
if signal a is asserted then
signal b is asserted for four clk;

Is it possible to accomplish the function by utilizing an SRL16, or is
there a better solution? Or should I simply create four delayed versions

of signal a, and OR them together to form signal b?

I'm working with a Virtex-2 device.

regards

 

[Rajeev]

Johan Bernspĺng <xjohbex@xfoix.se> wrote in message news:<ccjddj$39r$1@mercur.foi.se>...

Hi all,

What would be the optimal way, in terms of device utilization and
functionality, to exstend the length of the time a signal is asserted
from one clock cycle to four clock cycles. I.e.
[pseduo code:]
if signal a is asserted then
signal b is asserted for four clk;

Is it possible to accomplish the function by utilizing an SRL16, or is
there a better solution? Or should I simply create four delayed versions

of signal a, and OR them together to form signal b?

I'm working with a Virtex-2 device.

regards

I have used a 3-bit synchronous loadable counter for this task. MSB is high
for 4 ticks, and serves both as count-enable and output. You can count either
up or down.

This uses 3 registers. With 2 registers you could count 0,1,2,3,0=stop, output
would be OR of both registers and the input.

Now an SRL16 can be 16 registers, so as you say perhaps there is a clever
solution with this...

-rajeev-

 

[Guy Eschemann]

You could use a SRL16/DFF (with clock-enable and synchronous clear)
combination for this. The input pulse - which is high for one clock
cycle -sets the FF output, and a delayed version of this pulse clears
it after a number of clock cycles. The depth of the SLR16 sets the
length of the output pulse. Note that the output pulse is delayed by
one clock cycle with respect to the input pulse.
_______
| |
+--| SRL16 |------+
| |_______| |
| |
| ______ |
| | | |
short pulse -----+--|CE Q|----------- long pulse
| | |
1--|D | |
| | |
CLK--|> | |
| | |
+--|CLR | |
| |______| |
| |
+-----------------+

Regards,
Guy.

Johan Bernspĺng wrote:

Hi all,

What would be the optimal way, in terms of device utilization and
functionality, to exstend the length of the time a signal is asserted

from one clock cycle to four clock cycles. I.e.
[pseduo code:]
if signal_a is asserted then
signal_b is asserted for four clk;

Is it possible to accomplish the function by utilizing an SRL16, or
is
there a better solution? Or should I simply create four delayed
versions
of signal_a, and OR them together to form signal_b?

I'm working with a Virtex-2 device.

regards
--
-----------------------------------------------
Please remove the x's in the email address if
replying to me personally.

Johan Bernspĺng, xjohbex@xfoix.se