Extended VCD

[a]

Hello all
I have generated an extended vcd file for
a design which has 2 ports declared as std_logic_vector.
I tried to feed the vcd file to tetramax but it complaints
that it cannot find port x[3].

Anybody outthere who has solved that ?

 

[Andy Botterill]

In article <bu1hga$qgv$1@ulysses.noc.ntua.gr>, a <gxen@unipi.gr> writes

Hello all
I have generated an extended vcd file for

That's OK.

a design which has 2 ports declared as std_logic_vector.
I tried to feed the vcd file to tetramax but it complaints

Tetramax ,being an ATPG tool, does not use VCD files.

.

Anybody outthere who has solved that ?

--
Andy Botterill