Expression Width in Verilog?

[Shenli]

Hi all,

I am reading "Coding Guidelines for Datapath Synthesis" from Synopsys.
And I am confused with "expression width".

In below example, what's "expression width is 10 bits" mean? Is a and b
extended automatically? What circuit will be synthesized?

//--Verilog Start---
input [3:0] a;
input [7:0] b;
output [9:0] z;

assign z = a * b; // expression width is 10 bits
//--Verilog End---

Best regards,
Shenli

 

[Chris F Clark]

"Shenli" <zhushenli@gmail.com> writes:

Hi all,

I am reading "Coding Guidelines for Datapath Synthesis" from Synopsys.
And I am confused with "expression width".

In below example, what's "expression width is 10 bits" mean? Is a and b
extended automatically? What circuit will be synthesized?

//--Verilog Start---
input [3:0] a;
input [7:0] b;
output [9:0] z;

assign z = a * b; // expression width is 10 bits
//--Verilog End---

Best regards,
Shenli

While I expect Steve Sharp (or one of the other gurus) to correct me
if I get this wrong, I will take a stab at answering.

In the Verilog, the rule for an expression (whose width isn't
self-defining, for example a concatenate is self-defining, so that
target width doesn't matter), the width of the expression is computed
by looking at the operands (a and b in your case) and the destination
(z in your case) and determining the largest width, which is the 10
bits of z. So, the a * b expression needs to be 10 bits wide (to fill
z). The result of that, is that the operands (a and b) also need to
be 10 bits wide. The Verilog rule for widening unsigned expressions
is simply to prepent 0 bits on the left, as if one wrote {6'b0, a} and
{2'b0, b}. Thus, your code could have been written:

assign z = {6'b0, a} * {2'b0, b};

Now, the synthesizeser may lay down a 10 bit multiplier, or it may be
able to infer that some of those bits will always be 0 and lay down a
smaller one (actually, in this case the multiply results could in
theory overflow, so it will probably lay down a 10 bit one, although
it could lay down a 4 by 8 one (yielding 12 bits) and truncate the top
2 bits (as long as that calculates the correct value). What the
synthesizer will lay down will probably depend on your cell library.
The language simply requires that whatever it lays down calculates the
same results as the assignment with the concats in it.

Hope this helps,
-Chris

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Compiler Resources, Inc. Web Site : http://world.std.com/~compres
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