Expression sizing: VHDL vs. Verilog

[Martin Vass]

Hi all -

in VHDL, you can write code like this:

process is
variable A, B, C : SLV8;
variable i, j, k, m : integer;
begin
A := X"06";
B := X"90";
i := 7; j := 4; k := 3; m := 0;
C := B(i downto j) & A(k downto m); -- produces X"96"

In other words, you can have arbitrary expressions as slice indexes.
You can't do this in Verilog - the indexes must be constant (with a
minor extension for V-2001, which isn't relevant here).

This got me thinking about expression sizing in VHDL and Verilog. In
Verilog, expression sizes are statically determined, during
compilation. This makes it impossible to have variable slice
("part-select") indexes (although you can have one variable index in
V-2001, as long as the length is still static). The rules are complex
and not very logical, but at least the compiler always knows what the
size of any object is, and can do static error detection.

VHDL is very different. If you change one of the indexes in the code
above so that the concatentation doesn't contain 8 bits, then the code
will still compile and elaborate Ok, and will only produce an error at
runtime. The VHDL version is much more flexible, but presumably (a
lot?) less efficient.

My problem is that I don't actually understand what the rules are for
VHDL. There doesn't seem to be anywhere in the LRM that states
explicitly how objects are sized, extended, or truncated, or when,
during expression evaluation. Or have I just missed it? Can anyone
explain expression sizing, or point me to a reference?

Thanks -

-MV