explicit time units and timescale restore in verilog

[Anatoly Gelman]

Hi all,

Is there any way to explicitly declare a time unit delay that would work
regardless of the unit declaration of `timescale directive? Can I
effectively say something like "a = #1ns b;" Alternatively, is there a way
to programmatically obtain unit value declared from the timescale directive?
There is a function that reports timescale settings but it doesn't return
any values - just prints to display.

Related to the previous question, is there a way to "restore" effective
timescale before entering a verilog module? This would allow easy inclusion
foreign modules with different timescale without redeclaration of the
timescale.

any pointers are greatly appreciated.

Anatoly Gelman

 

[Srinivasan Venkataramanan]

Hi Anaoly,

"Anatoly Gelman" <agelman1@san.rr.com> wrote in message
news:CZQKa.125641$x67.5589520@twister.socal.rr.com...

Hi all,

Is there any way to explicitly declare a time unit delay that would work
regardless of the unit declaration of `timescale directive? Can I
effectively say something like "a = #1ns b;"

AFAIK the answer is NO -

Alternatively, is there a way
to programmatically obtain unit value declared from the timescale
directive?
There is a function that reports timescale settings but it doesn't return
any values - just prints to display.

Not sure what would that buy you, some time back I wrote a PLI to report
timescales on all modules in a design, which could be easily modified to
return the time unit, but not clear what you would do with it.

Related to the previous question, is there a way to "restore" effective
timescale before entering a verilog module?

Do you mean "reset the timescale"? There is a `resetall directive, but
that would reste ALL directives that were encountered till now.

I know that NCSIM recently added a new flag named -override_timescale with
ncelab (I guess in LDV 4.1), which would essentially override all time
scales in design, which simulator do you use?

HTH,
Srinivasan
--
Srinivasan Venkataramanan
Senior Verification Engineer
Software & Silicon Systems India Pvt Ltd. - an Intel company
Bangalore, India

http://www.noveldv.com http://www.deeps.org

I don't speak for Intel

 

[Alexander Gnusin]

integer NS
initial NS = timescale_to_integer(); // this is the function I am asking
for
wire (5*NS) a = b;

and this code would always work regardless of the `timescale declared before
this module in any environment.

can such a PLI be easily written? or is there a simpler way?

Anatoly Gelman

Hi Anatoly,
It seems that the simplest way to get this info is to write small PLI.
Here is the working example of such PLI for vcs:

pli.c
-----------------------------
#incude "veriuser.h"
int timeunit_calltf()
{
tf_putp(0, tf_gettimeunit);
return 0;
}

pli.tab
-----------------------------
$timeunit call=timeunit_calltf size=32 data=0


test.v
------------------------------
`timescale 1ns/1ns // change it
module test;
integer i;
initial begin
i = $timeunit;
$display("time unit is %d", i);
$finish;
end
endmodule


Run Line:
=========
gcc -I<vcs_path>/include/ -c pli.c -o pli.o
vcs -R test.v -P pli.tab pli.o

You 'll get timescale info according to the following table:

Integer Code Time Precision

2 100s
1 10s
0 1s
-1 100ms
-2 10ms
-3 1ms
-4 100us
-5 10us
-6 1us
-7 100ns
-8 10ns
-9 1ns
-10 100ps
-11 10ps
-12 1ps
-13 100fs
-14 10fs
-15 1fs


Regards,
Alexander Gnusin
www.TCLforEDA.net

 

[Anatoly Gelman]

Hi Alexander,

This is what I was looking for. Thanks much!

Anatoly Gelman

"Alexander Gnusin" <alexg@ottawa.com> wrote in message
news:a504dc86.0306300427.3f8522e9@posting.google.com...

integer NS
initial NS = timescale_to_integer(); // this is the function I am
asking
for
wire (5*NS) a = b;

and this code would always work regardless of the `timescale declared
before
this module in any environment.

can such a PLI be easily written? or is there a simpler way?

Anatoly Gelman

Hi Anatoly,
It seems that the simplest way to get this info is to write small PLI.
Here is the working example of such PLI for vcs:

pli.c
-----------------------------
#incude "veriuser.h"
int timeunit_calltf()
{
tf_putp(0, tf_gettimeunit);
return 0;
}

pli.tab
-----------------------------
$timeunit call=timeunit_calltf size=32 data=0


test.v
------------------------------
`timescale 1ns/1ns // change it
module test;
integer i;
initial begin
i = $timeunit;
$display("time unit is %d", i);
$finish;
end
endmodule


Run Line:
=========
gcc -I<vcs_path>/include/ -c pli.c -o pli.o
vcs -R test.v -P pli.tab pli.o

You 'll get timescale info according to the following table:

Integer Code Time Precision

2 100s
1 10s
0 1s
-1 100ms
-2 10ms
-3 1ms
-4 100us
-5 10us
-6 1us
-7 100ns
-8 10ns
-9 1ns
-10 100ps
-11 10ps
-12 1ps
-13 100fs
-14 10fs
-15 1fs


Regards,
Alexander Gnusin
www.TCLforEDA.net