Guest
Hi all,
My PhD research involves analysis and transformation of gate-level
netlists. I'm interested in verification mainly, but also in performing
netlist-to-netlist transformations of various kinds. I have a small,
simplistic hardware compiler of my own that has been fine for
experimentation so far, but as a next step I want to try applying my
ideas to pre-existing IP cores, so that means Verilog, realistically.
If I can avoid writing yet another Verilog front end this will save me
months of effort, so what I'm looking for is an (ideally free) Verilog
compiler that can go from a reasonable subset of the language to a very
vanilla netlist (just simple gates and flip flops).
It would seem that Icarus might be a good starting point, but it's not
clear from the web site whether I can get it to spit out such a
simplistic format without having to hack its back end. If there's no
alternative, I'd be happy to do that, but for obvious reasons I'd
rather spend my time hacking my own code (which will have to be GPL'd
eventually under the terms of my funding).
Since I'm sure that at least a few people reading this will have
similar requirements, I'm hoping that one of you can save me a bit of
time and pain by pointing me in the right direction.
If you're wondering what I'm up to, I'm basically working on several
things at the moment. One strand is using multivalued logics to analyse
the time behaviour of circuits more accurately than is possible with
conventional discrete time simulation. Another involves manipulation of
circuits at the netlist level using various transformation techniques,
including partial evaluation. Another involves using both partial
evaluation and SAT solvers together in order to do even fancier things.
I'd like to be able to grab a few public domain IP cores, get them into
a format my code can work with, and have some fun with them.
Thanks all,
Sarah Thompson,
Computer Laboratory,
University of Cambridge
My PhD research involves analysis and transformation of gate-level
netlists. I'm interested in verification mainly, but also in performing
netlist-to-netlist transformations of various kinds. I have a small,
simplistic hardware compiler of my own that has been fine for
experimentation so far, but as a next step I want to try applying my
ideas to pre-existing IP cores, so that means Verilog, realistically.
If I can avoid writing yet another Verilog front end this will save me
months of effort, so what I'm looking for is an (ideally free) Verilog
compiler that can go from a reasonable subset of the language to a very
vanilla netlist (just simple gates and flip flops).
It would seem that Icarus might be a good starting point, but it's not
clear from the web site whether I can get it to spit out such a
simplistic format without having to hack its back end. If there's no
alternative, I'd be happy to do that, but for obvious reasons I'd
rather spend my time hacking my own code (which will have to be GPL'd
eventually under the terms of my funding).
Since I'm sure that at least a few people reading this will have
similar requirements, I'm hoping that one of you can save me a bit of
time and pain by pointing me in the right direction.
If you're wondering what I'm up to, I'm basically working on several
things at the moment. One strand is using multivalued logics to analyse
the time behaviour of circuits more accurately than is possible with
conventional discrete time simulation. Another involves manipulation of
circuits at the netlist level using various transformation techniques,
including partial evaluation. Another involves using both partial
evaluation and SAT solvers together in order to do even fancier things.
I'd like to be able to grab a few public domain IP cores, get them into
a format my code can work with, and have some fun with them.
Thanks all,
Sarah Thompson,
Computer Laboratory,
University of Cambridge