V
Vivek
Guest
Hi,
I am facing a strange problem while doing Synthesis P&R of a
logic on "Excalibur" device (Altera EPXA10F1020C1 Package
FBGA1020) using "Quartus 4.0".
The logic written in Verilog is as below:-
---------------------------------------------------------
always @(negedge ResetN or posedge Clk1)
begin:logic1
if(ResetN == 1'b0)
begin
delayedReadyN1 <= 1'b1;
end
else
begin
delayedReadyN1 <= ReadyN;
end
end
always @(negedge ResetN or posedge Clk2)
begin:logic2
if(ResetN == 1'b0)
begin
delayedReadyN2 <= 1'b1;
end
else
begin
delayedReadyN2 <= ReadyN;
end
end
----------------------------------------------------------
ReadyN = is a signal generated in 'Clk1' domain.
Clk1 & Clk2 = are '80MHz' clocks.
ResetN = Asynchronous reset.
Quartus timing analyzer "doesn't give any timing violation" on these
but
when I do timing simulation using ModelSim (using .vo & .sdo files),
I observed that 'delayedReadyN2' changes as expected but
'delayedReadyN1' doesn't change at all even though input signal
'ReadyN' is changing!
ReadyN is generated in Clk1 domain is being assigned to
'delayedReadyN2' under Clk2 but not to 'delayedReadyN1'
under same clock Clk1.
I examined the cells in .vo file, which appears as below :-
----------------------------------------------------------
// atom is at LC5_12_I2
apex20ke_lcell \delayedReadyN1~I (
// Equation(s):
// delayedReadyN1 = DFFE(!\ReadyN~combout , \Clk1~combout ,
GLOBAL(\ResetN~combout ), , )
.dataa(vcc),
.datab(vcc),
.datac(vcc),
.datad(\ReadyN~combout ),
.cin(gnd),
.cascin(vcc),
.clk(\Clk1~combout ),
.aclr(!\ResetN~combout ),
.ena(vcc),
.sclr(gnd),
.sload(gnd),
.devclrn(devclrn),
.devpor(devpor),
.combout(),
.regout(delayedReadyN1),
.cout(),
.cascout());
// synopsys translate_off
defparam \delayedReadyN1~I .operation_mode = "normal";
defparam \delayedReadyN1~I .packed_mode = "false";
defparam \delayedReadyN1~I .lut_mask = "00FF";
defparam \delayedReadyN1~I .output_mode = "reg_only";
// synopsys translate_on
// atom is at LC2_13_R2
apex20ke_lcell \InstA|delayedReadyN2~I (
// Equation(s):
// \InstA|delayedReadyN2 = DFFE(!\ReadyN~combout ,
GLOBAL(\Clk2~combout ), GLOBAL(\ResetN~combout ), , )
.dataa(vcc),
.datab(vcc),
.datac(vcc),
.datad(\ReadyN~combout ),
.cin(gnd),
.cascin(vcc),
.clk(\Clk2~combout ),
.aclr(!\ResetN~combout ),
.ena(vcc),
.sclr(gnd),
.sload(gnd),
.devclrn(devclrn),
.devpor(devpor),
.combout(),
.regout(\InstA|delayedReadyN2 ),
.cout(),
.cascout());
// synopsys translate_off
defparam \InstA|delayedReadyN2~I .operation_mode = "normal";
defparam \InstA|delayedReadyN2~I .packed_mode = "false";
defparam \InstA|delayedReadyN2~I .lut_mask = "00FF";
defparam \InstA|delayedReadyN2~I .output_mode = "reg_only";
// synopsys translate_on
----------------------------------------------------------
I checked all the signals related to the cells & found to be
exactly as expected.
What can be the problem?
Best Regards,
Vivek
I am facing a strange problem while doing Synthesis P&R of a
logic on "Excalibur" device (Altera EPXA10F1020C1 Package
FBGA1020) using "Quartus 4.0".
The logic written in Verilog is as below:-
---------------------------------------------------------
always @(negedge ResetN or posedge Clk1)
begin:logic1
if(ResetN == 1'b0)
begin
delayedReadyN1 <= 1'b1;
end
else
begin
delayedReadyN1 <= ReadyN;
end
end
always @(negedge ResetN or posedge Clk2)
begin:logic2
if(ResetN == 1'b0)
begin
delayedReadyN2 <= 1'b1;
end
else
begin
delayedReadyN2 <= ReadyN;
end
end
----------------------------------------------------------
ReadyN = is a signal generated in 'Clk1' domain.
Clk1 & Clk2 = are '80MHz' clocks.
ResetN = Asynchronous reset.
Quartus timing analyzer "doesn't give any timing violation" on these
but
when I do timing simulation using ModelSim (using .vo & .sdo files),
I observed that 'delayedReadyN2' changes as expected but
'delayedReadyN1' doesn't change at all even though input signal
'ReadyN' is changing!
ReadyN is generated in Clk1 domain is being assigned to
'delayedReadyN2' under Clk2 but not to 'delayedReadyN1'
under same clock Clk1.
I examined the cells in .vo file, which appears as below :-
----------------------------------------------------------
// atom is at LC5_12_I2
apex20ke_lcell \delayedReadyN1~I (
// Equation(s):
// delayedReadyN1 = DFFE(!\ReadyN~combout , \Clk1~combout ,
GLOBAL(\ResetN~combout ), , )
.dataa(vcc),
.datab(vcc),
.datac(vcc),
.datad(\ReadyN~combout ),
.cin(gnd),
.cascin(vcc),
.clk(\Clk1~combout ),
.aclr(!\ResetN~combout ),
.ena(vcc),
.sclr(gnd),
.sload(gnd),
.devclrn(devclrn),
.devpor(devpor),
.combout(),
.regout(delayedReadyN1),
.cout(),
.cascout());
// synopsys translate_off
defparam \delayedReadyN1~I .operation_mode = "normal";
defparam \delayedReadyN1~I .packed_mode = "false";
defparam \delayedReadyN1~I .lut_mask = "00FF";
defparam \delayedReadyN1~I .output_mode = "reg_only";
// synopsys translate_on
// atom is at LC2_13_R2
apex20ke_lcell \InstA|delayedReadyN2~I (
// Equation(s):
// \InstA|delayedReadyN2 = DFFE(!\ReadyN~combout ,
GLOBAL(\Clk2~combout ), GLOBAL(\ResetN~combout ), , )
.dataa(vcc),
.datab(vcc),
.datac(vcc),
.datad(\ReadyN~combout ),
.cin(gnd),
.cascin(vcc),
.clk(\Clk2~combout ),
.aclr(!\ResetN~combout ),
.ena(vcc),
.sclr(gnd),
.sload(gnd),
.devclrn(devclrn),
.devpor(devpor),
.combout(),
.regout(\InstA|delayedReadyN2 ),
.cout(),
.cascout());
// synopsys translate_off
defparam \InstA|delayedReadyN2~I .operation_mode = "normal";
defparam \InstA|delayedReadyN2~I .packed_mode = "false";
defparam \InstA|delayedReadyN2~I .lut_mask = "00FF";
defparam \InstA|delayedReadyN2~I .output_mode = "reg_only";
// synopsys translate_on
----------------------------------------------------------
I checked all the signals related to the cells & found to be
exactly as expected.
What can be the problem?
Best Regards,
Vivek