Event

[Michael]

hello
I'm trying to assign a value to a signal, LAST, when there's an event
on DEV_DATA and count <= 0, the following is the code:
out_logic: process(current_state, DEV_DATA, DEV_ADDR, DEV_RTYP,
DEV_RDY, DEV_GRNT,
FRAME, C_BE, IRDY, TRDY, DEVSEL, AD)
begin
case current_state is
when "00010" =>
IRDY <= '1';
if DEV_DATA'event and count <= 1 then
LAST <= '1';
else
LAST <= '0';
...

I'm getting a synthesis error saying "unsupported Clock statement".
DEV_DATA is declared as a port, inout std_logic_vector(7 downto 0) and
count is signal count : std_logic_vector(2 downto 0).

please help

thank you

 

[Ralf Hildebrandt]

Hi Michael!

I'm trying to assign a value to a signal, LAST, when there's an event
on DEV_DATA and count <= 0, the following is the code:

Think about a different approach. DEV_DELTA'event ist not
synthesizeable. You are allowed to trigger eigther on the rising_edge
oder on the falling_edge with a standard flipflop. Dual-edge-flipflops
are today not supported by synthesis. - However, dual-edge - behavior is
possible, but tricky.

out_logic: process(current_state, DEV_DATA, DEV_ADDR, DEV_RTYP,
DEV_RDY, DEV_GRNT,
FRAME, C_BE, IRDY, TRDY, DEVSEL, AD)
begin
case current_state is
when "00010" =
IRDY <= '1';
if DEV_DATA'event and count <= 1 then
LAST <= '1';
else
LAST <= '0';
...

I'm getting a synthesis error saying "unsupported Clock statement".

No 'event - detection inside a case-statement is allowed.

The single-edge solution is the following (standart flipflop):

process(DEV_DELTA)
begin
if rising_edge(DEV_DELTA) then
-- if falling_edge(DEV_DELTA) then -- alternative
if (current_state="00010") then
if(AND count<=1) then
LAST<='1';
else LAST<='0';
end if;
end if;
endif;
end process;



For dual-edge-behavior it is nessecary to have two flipflops - one for
each edge - and a mux, that chooses, which flipflop's data is valid. The
mux-control is very tricky and because of this mux, the final signal is
hazarderous.
-> Think about a differnent approach. If your approach is the _only_
solution, you may think about the dual-edge-behavior.


Ralf

 

[Jim Lewis]

Michael,
You are writing software and for synthesis you need to
code hardware. You need to re-think your logic in terms
of hardware and good hardware design practices.

To detect if DEV_DATA has changed, you need to compare the
current value of DEV_DATA with the previous value of DEV_DATA.
To get the previous value of DEV_DATA you will need a
register. You may need an additional register on Last for timing.

Cheers,
Jim Lewis
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:Jim@SynthWorks.com
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~


Michael wrote:

hello
I'm trying to assign a value to a signal, LAST, when there's an event
on DEV_DATA and count <= 0, the following is the code:
out_logic: process(current_state, DEV_DATA, DEV_ADDR, DEV_RTYP,
DEV_RDY, DEV_GRNT,
FRAME, C_BE, IRDY, TRDY, DEVSEL, AD)
begin
case current_state is
when "00010" =
IRDY <= '1';
if DEV_DATA'event and count <= 1 then
LAST <= '1';
else
LAST <= '0';
...

I'm getting a synthesis error saying "unsupported Clock statement".
DEV_DATA is declared as a port, inout std_logic_vector(7 downto 0) and
count is signal count : std_logic_vector(2 downto 0).

please help

thank you