ethernet mac

[dan]

Hi,

i'm new to verilog(as in i have < 1 hour experience), but i have
experience with VHDL.

I'm trying to implement an ethernet MAC in a VHDL program and the only
free one i can find is the open cores verilog one(i have no powerPC
etc). First off has anyone used this before and could help me drive it?


The core comes with two top level modules, eth_top and eth_cop, the
core makes use of the opencores wishbone interface which i've looked at
but seems to be just an excuse for core designers to not document their
core properly. Has anyone used this before and could tell me how to set
the thing up?

I've been trying myself and made some progress.
I looked at the test benches(to see how they drive the modules) and it
came with 2 other modules, memory and host...however these have errors
which i don't have the verilog knowledge to deal with.

one was near the beginning of an always:

1 always @ (posedge wb_clk_i)
2 begin
3 if(wb_cyc_i & wb_stb_i)
4 begin
5 repeat(1) @ (posedge wb_clk_i); <-------------- this
line
6 .....

i interpeted this as,
line 1: on rising_edge of wb_clk_i
line 5: on rising_edge of wb_clk_i


it would be silly to have nested posedges(if it is working like that)
especially on the same clock
so i took out the "@ (posedge wb_clk_i)" on line 5 and it works.

Is this correct or have i changed the functionality of the program by
doing this.

another error is again an always but this time it's to do with the
sensitivity list

always @ (m1_in_progress or m1_wb_adr_i or s1_wb_ack_i or s2_wb_ack_i
or s1_wb_dat_i or s2_wb_dat_i or `M1_ADDRESSED_S1 or `M1_ADDRESSED_S2)


error Unexpected event in always block sensitivity list

the answer database says "XST also reports the above error if the
sensitivity list is mixed between edge-sensitive and level-sensitive"

anyone know what that means? what is an edge sensitive and level
sensitive signal?

Thanks

Dan

 

[gabor]

dan wrote:

Hi,

i'm new to verilog(as in i have < 1 hour experience), but i have
experience with VHDL.

I'm trying to implement an ethernet MAC in a VHDL program and the only
free one i can find is the open cores verilog one(i have no powerPC
etc). First off has anyone used this before and could help me drive it?


The core comes with two top level modules, eth_top and eth_cop, the
core makes use of the opencores wishbone interface which i've looked at
but seems to be just an excuse for core designers to not document their
core properly. Has anyone used this before and could tell me how to set
the thing up?

I've been trying myself and made some progress.
I looked at the test benches(to see how they drive the modules) and it
came with 2 other modules, memory and host...however these have errors
which i don't have the verilog knowledge to deal with.

one was near the beginning of an always:

1 always @ (posedge wb_clk_i)
2 begin
3 if(wb_cyc_i & wb_stb_i)
4 begin
5 repeat(1) @ (posedge wb_clk_i); <-------------- this
line
6 .....

i interpeted this as,
line 1: on rising_edge of wb_clk_i
line 5: on rising_edge of wb_clk_i

Actually line 5 should cause another clock cycle delay. If
you run this in ModelSim you should see it. However
synthesis tools don't generally support this type of syntax.

it would be silly to have nested posedges(if it is working like that)
especially on the same clock
so i took out the "@ (posedge wb_clk_i)" on line 5 and it works.

Is this correct or have i changed the functionality of the program by
doing this.

another error is again an always but this time it's to do with the
sensitivity list

always @ (m1_in_progress or m1_wb_adr_i or s1_wb_ack_i or s2_wb_ack_i
or s1_wb_dat_i or s2_wb_dat_i or `M1_ADDRESSED_S1 or `M1_ADDRESSED_S2)


error Unexpected event in always block sensitivity list

the answer database says "XST also reports the above error if the
sensitivity list is mixed between edge-sensitive and level-sensitive"

anyone know what that means? what is an edge sensitive and level
sensitive signal?

The last two arguments in the sensitivity list are macros. You need
to look at the definitions to tell whether they are level or edge
sensitive. Edge sensitive items look like "posedge sig_name"
while level sensitive items are just "sig_name".

It looks as if you're trying to synthesize code that was written
as a test bench. If you need this functionality in your design
you may be better off re-writing it in a language you understand.
If not, just use them for simulation.

Thanks

Dan

 

[Ajeetha]

Looks to me like you are passing testbench files to a synthesis tool -
XST.

It doesn't matter whether it is Verilog or VHDL here.

Regards
Ajeetha, CVC
www.noveldv.com

 

[dan]

ahhh i see

thanks