A
ashu
Guest
after compiling and wrting the design i am getting an error as follows
Warning: There is a data discrepancy between synopsys database and the
output file. (VHDL-286)
what cud be the reason ?
thanks
Warning: There is a data discrepancy between synopsys database and the
output file. (VHDL-286)
what cud be the reason ?
thanks