error

A

ashu

Guest
after compiling and wrting the design i am getting an error as follows

Warning: There is a data discrepancy between synopsys database and the
output file. (VHDL-286)

what cud be the reason ?

thanks
 
Hi,
Provide more details as to:

Is this simulation or synthesis?
Which tool?

As this is a Warning, what happens after this? Are you still able to go
thro' the flow?

Ajeetha, CVC
www.noveldv.com
 
I believe the error code VHDL-286 is documented in their docs, you may
get lucky if you look in that.

Ajeetha, CVC
www.noveldv.com
 
ashu wrote:

Warning: There is a data discrepancy between synopsys database and the
output file. (VHDL-286)
http://www.google.com/search?q=Warning+VHDL-286+data+discrepancy
 

Welcome to EDABoard.com

Sponsor

Back
Top