error

K

Kausi

Guest
I get the following error for the particular line given below-

Code- always @(state or posedge Valid or posedge Restart)
begin
case(state)

3'b000 : begin if(Valid)
next_state<=3'b001; end
3'b001 : begin if(Valid)
next_state<=3'b010;
else Seg1=7'b1111001; end
3'b010 : begin if(Valid)
next_state<=3'b011;
else Seg1=7'b0100100; end
3'b011 : begin if(Valid)
next_state<=3'b100;
else Seg1=7'b0110000;
end
3'b100 : begin Done<=1'b1;
Seg1=7'b0011011;
next_state<=3'b101; end
3'b101 : begin if(Restart)
next_state<=3'b000;
else Seg1=7'b0010010; end
endcase
end

Error (10122): Verilog HDL Event Control error at safe.v(16): mixed
single- and double-edge expressions are not supported.

When i check up the help section it says i cant use a positive edge
controlled and a negative edge controlled signal in the event list. A
further suggession is given to split the event control into multiple
statements. How can i achieve that ?
 
On Sat, 8 Nov 2008 07:52:06 -0800 (PST), Kausi
<kauser.johar@gmail.com> wrote:

I get the following error for the particular line given below-

Code- always @(state or posedge Valid or posedge Restart)
...
Error (10122): Verilog HDL Event Control error at safe.v(16): mixed
single- and double-edge expressions are not supported.

When i check up the help section it says i cant use a positive edge
controlled and a negative edge controlled signal in the event list. A
further suggession is given to split the event control into multiple
statements. How can i achieve that ?
Click to expand...
Assuming you have a clock which controls Valid and Restart signals,
here is what you can do:

always @(posedge clk)
begin
validp <= valid;
restartp <= restart;
end

wire validposedge = !validp & valid;
wire restartposedge = !restartp & restart;

always @(state or validposedge or restartposedge)
....


Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services
http://www.dspia.com
 
I have another question-

if i had only clock in the sensitivity or event list,will it still
execute the case statements ?
 
On Sat, 8 Nov 2008 10:04:38 -0800 (PST), Kausi
<kauser.johar@gmail.com> wrote:

Iam pasting my complete code below- The state does not change. Can
anyone explain me why ?
Click to expand...
It's most probably because you're not giving state an initial value
which causes the case statement not to take any branches. For starters
add
initial state = 3'b000;
to your code and retry. Later you can work on getting this to happen
in real hardware (hint use a reset signal).
If this is not what ails your design, answer these questions: Are you
simulating this design? Do you have a clock? Are you generating either
of the Valid or Restart signals? Does next_state change at all?
In other words, just fire up a simulator & debug.

Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services
http://www.dspia.com
 
Iam pasting my complete code below- The state does not change. Can
anyone explain me why ?

module safe(Code, Valid, Seg1, Seg2,Clk,Restart,Done);

input [3:0] Code;
input Valid,Restart;
input Clk;
output [6:0] Seg1;
output [6:0] Seg2;
output Done;

reg [2:0] state;
reg [2:0] next_state;
reg [6:0] Seg1;
reg [6:0] Seg2;
reg Done;
integer count;



always @(state or Valid or Restart)
begin
case(state)

3'b000 : begin if(Valid)
next_state<=3'b001; end

3'b001 : begin if(Valid)
next_state<=3'b010;
else count=0; end

3'b010 : begin if(Valid)
next_state<=3'b011;
else count=1; end

3'b011 : begin if(Valid)
next_state<=3'b100;
else
count=2;end

3'b100 : begin Done<=1'b1;
count=3;
next_state<=3'b101; end

3'b101 : begin if(Restart)
next_state<=3'b000;
else count=4; end
endcase
end

always @(count)
begin
case(count)
0 : Seg1<=7'b1111001;
1 : Seg1<=7'b0100100;
2 : Seg1<=7'b0110000;
3 : Seg1<=7'b0011011;
4 : Seg1<=7'b0010010;
default : Seg1<=7'b0101010;
endcase
end
always @(posedge Clk)
begin state<=next_state; end

always @(Code)
begin
case(Code)
4'b0001 : Seg2=7'b1111001; // 1
4'b0010 : Seg2=7'b0100100; // 2
4'b0011 : Seg2=7'b0110000; // 3
4'b0100 : Seg2=7'b0011011; // 4
4'b0101 : Seg2=7'b0010010; // 5
4'b0110 : Seg2=7'b0000010; // 6
4'b0111 : Seg2=7'b0111000; // 7
4'b1000 : Seg2=7'b0000000; // 8
4'b1001 : Seg2=7'b0010000; // 9
4'b1010 : Seg2=7'b0001000; // A
4'b1011 : Seg2=7'b0000000; // B
4'b1100 : Seg2=7'b1000110; // C
4'b1101 : Seg2=7'b1000000; // D
4'b1110 : Seg2=7'b0000110; // E
4'b1111 : Seg2=7'b0001110; // F
4'b0000 : Seg2=7'b1000000; // 0
default : Seg2=7'b0001001; // Displayed as H
endcase
end
endmodule
 
Well i did add the initial state value, it doesnt help.

1. Yes iam simulating the design using Quartus2.
2. Iam using a clock, and both the valid and reset signal are input at
the time required.

I use a similar style of writing in VHDL, and codes work absolutely
fine. Wondering is it the simulator causing the problem !!


Regards,
Kauser.
 
On Sat, 8 Nov 2008 12:45:56 -0800 (PST), Kausi wrote:

Well i did add the initial state value, it doesnt help.

1. Yes iam simulating the design using Quartus2.

2. Iam using a clock, and both the valid and reset signal are input at
the time required.
Click to expand...
What reset signal? I didn't see one.

I use a similar style of writing in VHDL, and codes work absolutely
fine.
Click to expand...
Your code wouldn't get past any code review I was
involved in....
* There's no reset on the state register.
* Your combinational next-state process creates
asynchronous latches on next_state, Done and count.
This is inexcusable. It's broken, and provides
a perfect example of why two-process state
machines are so sucky.

It's likely that your FSM worked in VHDL because
you used an enumerated type for the state, and
signals of enum type in VHDL simulation will
always reset to their left-most value. What
happens in the hardware is anyone's guess,
unless you reset the state register properly.
As far as the latch business is concerned,
remember that the state register captures
next_state on EVERY clock cycle, not just
the cycles on which you update next_state.
So next_state should be defaulted to current
state at the top of your next-state process.
What is supposed to happen to "count" and "Done"
I can only guess, but the asynch latch is an
evil way to do it whatever it is.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
 
On Nov 8, 4:43 pm, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
wrote:
On Sat, 8 Nov 2008 12:45:56 -0800 (PST), Kausi wrote:
Well i did add the initial state value, it doesnt help.

1. Yes iam simulating the design using Quartus2.
2. Iam using a clock, and both the valid and reset signal are input at
the time required.

What reset signal?  I didn't see one.

I use a similar style of writing in VHDL, and codes work absolutely
fine.

Your code wouldn't get past any code review I was
involved in....  
* There's no reset on the state register.
* Your combinational next-state process creates
  asynchronous latches on next_state, Done and count.
  This is inexcusable.  It's broken, and provides
  a perfect example of why two-process state
  machines are so sucky.

It's likely that your FSM worked in VHDL because
you used an enumerated type for the state, and
signals of enum type in VHDL simulation will
always reset to their left-most value.  What
happens in the hardware is anyone's guess,
unless you reset the state register properly.
As far as the latch business is concerned,
remember that the state register captures
next_state on EVERY clock cycle, not just
the cycles on which you update next_state.
So next_state should be defaulted to current
state at the top of your next-state process.
What is supposed to happen to "count" and "Done"
I can only guess, but the asynch latch is an
evil way to do it whatever it is.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Click to expand...
The register "next_state" forms a latch in this design. So
even with an initial value for "state", unless "Valid" is
active for the first clock cycle "state" will go to X
immediately and stay there.

Try something like:

module safe(Code, Valid, Seg1, Seg2,Clk,Restart,Done);

input [3:0] Code;
input Valid,Restart;
input Clk;
output [6:0] Seg1;
output [6:0] Seg2;
output Done;

reg [2:0] state;
reg [2:0] next_state;
reg [6:0] Seg1;
reg [6:0] Seg2;
reg Done;
integer count;

initial state = 3'b000;
always @(state or Valid or Restart)
begin
next_state = state; // Default to no change if not Valid
case(state)

3'b000 : begin if(Valid)
next_state=3'b001; end

3'b001 : begin if(Valid)
next_state=3'b010;
else count=0; end

3'b010 : begin if(Valid)
next_state=3'b011;
else count=1; end

3'b011 : begin if(Valid)
next_state=3'b100;
else count=2;end

3'b100 : begin Done<=1'b1;
count=3;
next_state=3'b101; end

3'b101 : begin if(Restart)
next_state=3'b000;
else count=4; end
endcase
end

always @(count)
begin
case(count)
0 : Seg1=7'b1111001;
1 : Seg1=7'b0100100;
2 : Seg1=7'b0110000;
3 : Seg1=7'b0011011;
4 : Seg1=7'b0010010;
default : Seg1=7'b0101010;
endcase
end
always @(posedge Clk)
begin state<=next_state; end

always @(Code)
begin
case(Code)
4'b0001 : Seg2=7'b1111001; // 1
4'b0010 : Seg2=7'b0100100; // 2
4'b0011 : Seg2=7'b0110000; // 3
4'b0100 : Seg2=7'b0011011; // 4
4'b0101 : Seg2=7'b0010010; // 5
4'b0110 : Seg2=7'b0000010; // 6
4'b0111 : Seg2=7'b0111000; // 7
4'b1000 : Seg2=7'b0000000; // 8
4'b1001 : Seg2=7'b0010000; // 9
4'b1010 : Seg2=7'b0001000; // A
4'b1011 : Seg2=7'b0000000; // B
4'b1100 : Seg2=7'b1000110; // C
4'b1101 : Seg2=7'b1000000; // D
4'b1110 : Seg2=7'b0000110; // E
4'b1111 : Seg2=7'b0001110; // F
4'b0000 : Seg2=7'b1000000; // 0
default : Seg2=7'b0001001; // Displayed as H
endcase
end
endmodule
 
Kausi wrote:
Well i did add the initial state value, it doesnt help.

1. Yes iam simulating the design using Quartus2.
Click to expand...
Quartus is not a simulator.
Try modelsim.

-- Mike Treseler
 
Hello,

Based on the feedback i have modified the code shown below- It works
fine now.

module safe(Code, Valid, Seg1, Seg2,Clk,Restart,Done);

input [3:0] Code;
input Valid,Restart;
input Clk;
output [6:0] Seg1;
output [6:0] Seg2;
output Done;

reg [2:0] state;
reg [2:0] next_state;
reg [6:0] Seg1;
reg [6:0] Seg2;
reg Done;
reg [2:0] count;


initial begin state= 3'b000;
count=3'b000;
Done<=1'b0; end

always @(state or count)
begin
case(state)

3'b000 : begin Done<=1'b0;
if(count==3'b001) next_state<=3'b001;
else next_state<=3'b000; end

3'b001 : begin Done<=1'b0;
if(count==3'b010)
next_state<=3'b010;
else next_state<=3'b001; end

3'b010 : begin Done<=1'b0;
if(count==3'b011)
next_state<=3'b011;
else next_state<=3'b010; end

3'b011 : begin Done<=1'b0;
if(count==3'b100)
next_state<=3'b100;
else
next_state<=3'b011;end

3'b100 : begin Done<=1'b1;
if(count==3'b000)
next_state<=3'b000;
else next_state<=3'b100; end
endcase
end

always @(posedge Valid or posedge Restart)
begin
if(Restart) count=3'b000;
else count=count+1'b1;
end

always @(count)
begin
case(count)
3'b001 : Seg1<=7'b1111001;
3'b010 : Seg1<=7'b0100100;
3'b011 : Seg1<=7'b0110000;
3'b100 : Seg1<=7'b0011011;
//5 : Seg1<=7'b0010010;
default : Seg1<=7'b0101010;
endcase
end
always @(posedge Clk)
begin state<=next_state; end

always @(Code)
begin
case(Code)
4'b0001 : Seg2=7'b1111001; // 1
4'b0010 : Seg2=7'b0100100; // 2
4'b0011 : Seg2=7'b0110000; // 3
4'b0100 : Seg2=7'b0011011; // 4
4'b0101 : Seg2=7'b0010010; // 5
4'b0110 : Seg2=7'b0000010; // 6
4'b0111 : Seg2=7'b0111000; // 7
4'b1000 : Seg2=7'b0000000; // 8
4'b1001 : Seg2=7'b0010000; // 9
4'b1010 : Seg2=7'b0001000; // A
4'b1011 : Seg2=7'b0000000; // B
4'b1100 : Seg2=7'b1000110; // C
4'b1101 : Seg2=7'b1000000; // D
4'b1110 : Seg2=7'b0000110; // E
4'b1111 : Seg2=7'b0001110; // F
4'b0000 : Seg2=7'b1000000; // 0
default : Seg2=7'b0001001; // Displayed as H
endcase
end
endmodule
 
After completing the above, iam moving forward to adding more
complexity to my design. This time i need to use a memory for some
calculations. I have declared a register as follows- reg [3:0]
mema[0:3];

This is basically done as i need to save the value of signal Code(for
all the states) into memory. As expected with my style of writing( and
iam still trying to improve it), it forms several latches. Any work
around please. Can someone explain what needs to be done to prevent
latches always. Find my new code snipet below. The remaining code is
as above.

reg [3:0] mema[0:3];
always @(state or count or Code)
begin
case(state)

3'b000 : begin Done<=1'b0;
if(count==3'b001) next_state<=3'b001;
else next_state<=3'b000; end

3'b001 : begin Done<=1'b0;
mema[0]<=Code;
if(count==3'b010)
next_state<=3'b010;
else next_state<=3'b001; end

3'b010 : begin Done<=1'b0;
mema[1]<=Code;
if(count==3'b011)
next_state<=3'b011;
else next_state<=3'b010; end

3'b011 : begin Done<=1'b0;
mema[2]<=Code;
if(count==3'b100)
next_state<=3'b100;
else
next_state<=3'b011;end

3'b100 : begin Done<=1'b1;
mema[3]<=Code;
if(count==3'b000)
next_state<=3'b000;
else next_state<=3'b100; end
endcase
end

I know that in the states, not all memory values are receiving values
which may be one reason to form a latch. But is memory to function
that way ? Iam really confused.
 
Have you tried initializing the value of next_state in that loop to the
current value of state? I'd expect that to reduce the number of
latches.
..
"Kausi" <kauser.johar@gmail.com> wrote in message
news:6257b9db-0dba-430d-9c57-5f7695f16ec5@w1g2000prk.googlegroups.com...
After completing the above, iam moving forward to adding more
complexity to my design. This time i need to use a memory for some
calculations. I have declared a register as follows- reg [3:0]
mema[0:3];

This is basically done as i need to save the value of signal Code(for
all the states) into memory. As expected with my style of writing( and
iam still trying to improve it), it forms several latches. Any work
around please. Can someone explain what needs to be done to prevent
latches always. Find my new code snipet below. The remaining code is
as above.

reg [3:0] mema[0:3];
always @(state or count or Code)
begin
case(state)

3'b000 : begin Done<=1'b0;
if(count==3'b001) next_state<=3'b001;
else next_state<=3'b000; end

3'b001 : begin Done<=1'b0;
mema[0]<=Code;
if(count==3'b010)
next_state<=3'b010;
else next_state<=3'b001; end

3'b010 : begin Done<=1'b0;
mema[1]<=Code;
if(count==3'b011)
next_state<=3'b011;
else next_state<=3'b010; end

3'b011 : begin Done<=1'b0;
mema[2]<=Code;
if(count==3'b100)
next_state<=3'b100;
else
next_state<=3'b011;end

3'b100 : begin Done<=1'b1;
mema[3]<=Code;
if(count==3'b000)
next_state<=3'b000;
else next_state<=3'b100; end
endcase
end

I know that in the states, not all memory values are receiving values
which may be one reason to form a latch. But is memory to function
that way ? Iam really confused.
Click to expand...
 
On Sat, 8 Nov 2008 18:41:42 -0800 (PST), Kausi
<kauser.johar@gmail.com> wrote:

Can someone explain what needs to be done to prevent
latches always.
Click to expand...
Latches are generated when in a block statement not all branches
assign values to a register. The reason can be an else branch missing
in an "if" statement or a case statement not decoded. In your
next_state logic, the best way to remove the latch is to assign
next_state to current state at the top of the always block so if
next_state is not assigned later it will keep the current state which
can be accomplish without any memory as it can be done only with a mux
from the output of the state register. So only state register will
generate memory (a DFF most probably) and all the next_state
calculation will be combinational.

ie:
always @(state, count, ...)
begin
next_state = state;

case(state)
3'b000: next_state = ???
....
end

Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services
http://www.dspia.com
 
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