error

[raghu]

module simp();
output [3:0] s;
reg [3:0] s;
reg [5:0] k;
initial
s = k[5-:4];
endmodule

when I compile this program i get an error as: near ":": expecting:
IDENT
can anyone please tell where the program has gone wrong? how to remove
the error?.

Thanks a ton in advance.

Regards,
Raghu

 

[Jonathan Bromley]

On 12 Jul 2006 05:29:41 -0700, raghu
<raghujindia@gmail.com> wrote:

module simp();
output [3:0] s;
reg [3:0] s;
reg [5:0] k;
initial
s = k[5-:4];
endmodule

when I compile this program i get an error as: near ":": expecting:
IDENT
can anyone please tell where the program has gone wrong?

Check you have Verilog-2001 compilation enabled. Indexed
part select [n-:m] is a Verilog-2001 feature. It seems that
the compiler thinks that "5-" is the beginning of an expression.

By the way, there's no need to use this feature if your part
select has constant bounds: your code is the same as

s = k[5:2];

but I guess you knew that, and are in fact doing something
more complicated?
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[ABC]

Hi Raghu,
Based on your example, should be missing port list.
module simp(s);
output [3:0] s;
reg [3:0] s;
reg [5:0] k;
initial
s = k[5-:4];
endmodule
Best ergards,
ABC


raghu wrote:

module simp();
output [3:0] s;
reg [3:0] s;
reg [5:0] k;
initial
s = k[5-:4];
endmodule

when I compile this program i get an error as: near ":": expecting:
IDENT
can anyone please tell where the program has gone wrong? how to remove
the error?.

Thanks a ton in advance.

Regards,
Raghu