error Xst:899

[AnamDar]

I am receiving this error in xilinx
ERROR:Xst:899 - "../../rtl/dff.v" line 7: The logic for <qout> does no
match a known FF or Latch template.

The code being synthesizd is:

module dff(output reg qout, input clok, rst,d,enf);
always @(posedge clok or negedge rst)
begin
if(enf)
begin
if(rst)
qout<=0;
else
qout<=d;
end
end

endmodule


can anyone guide me where i am going wrong?



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[GaborSzakacs]

AnamDar wrote:

I am receiving this error in xilinx
ERROR:Xst:899 - "../../rtl/dff.v" line 7: The logic for <qout> does not
match a known FF or Latch template.

The code being synthesizd is:

module dff(output reg qout, input clok, rst,d,enf);
always @(posedge clok or negedge rst)
begin
if(enf)
begin
if(rst)
qout<=0;
else
qout<=d;
end
end

endmodule


can anyone guide me where i am going wrong?



---------------------------------------
Posted through http://www.FPGARelated.com

What are you trying to do with signal "enf"? The way
you coded it, enf overrides the asynchronous reset as
well as the clock. Also since you coded reset as a
negedge signal, it should be tested for being low rather
than high. If "enf" is supposed to be a clock enable
it should be part of the else clause like:

always @ (posedge clok or negedge rst)
begin
if (!rst) // active low async reset
qout <= 0;
else if (enf) // enf used as a clock enable
qout <= d;
end

--
Gabor