Error with Hierarky editor

[Kuan Zhou]

Hi,
When I used hierarky editor to do postlayout simulations, I got very
strange errors. Every time when I switch the block view from schematic
to analog_extracted, the spectre simulator gives me the warning message
like:
Fatal error found by spectreduring initial setup.
Arithmetic exception.

I am using IC 5.0.33.021504. I genertated my analog_extracted view by
choosing Rparasitics and CDS_coeffgen_cap.

Thank you!



sincerely
-------------
Kuan Zhou
ECSE department

 

[Partha]

This might not be to do with the hierarchy editor, There are many
reasons that might cause arithmetic exception errors.
what analysis are you running?
Refer to https://sourcelink.cadence.com on more info

Source link: 1844664

Some possible causes of Arithmetic Exception are:

- Divide by zero or an overflow caused by a large exponent

- The simulation goes into an unphysical region

- Devices producing huge, unrealistic currents

- Changing states instantaneously in "if" statements in verilog-A

- Discontinuous models in verilog-A


To get around the issue, you can try the following:

- Change the tolerances (reltol, iabstol, etc).

- If you've set currents=all selected, turn it off (a smaller
set of equations will be used by the simulator) and see if the
simulation will converge.



Kuan Zhou <zhouk@rpi.edu> wrote in message news:<Pine.SOL.3.96.1040329105928.29977A-100000@vcmr-86.server.rpi.edu>...

Hi,
When I used hierarky editor to do postlayout simulations, I got very
strange errors. Every time when I switch the block view from schematic
to analog_extracted, the spectre simulator gives me the warning message
like:
Fatal error found by spectreduring initial setup.
Arithmetic exception.

I am using IC 5.0.33.021504. I genertated my analog_extracted view by
choosing Rparasitics and CDS_coeffgen_cap.

Thank you!



sincerely
-------------
Kuan Zhou
ECSE department