Error while extracting layout

[kamesh]

Dear all,

I am using cadence 5.0.33 and DRC runs fine without any errors (but
there are some warnings like "layer purpose fair does not exist in the
tech file"). I am using HCMOS8D (0.18u tech) from ST microelectronics.
When I try to extract the layout I get the following error.

"Errors exist in the rules file
"/sw/cadence/libraries/HCMOS8D//DK_hcmos8d_4.0/Opus/DK_hcmos8d/divaEXT.rul".

Could you please throw some light on where the problem could be.

Thanks and Regards,
Kamesh.

 

[Edward Kalenda]

On 18 Oct 2006 05:54:49 -0700, "kamesh" <vkamesh@gmail.com> wrote:

Dear all,

I am using cadence 5.0.33 and DRC runs fine without any errors (but
there are some warnings like "layer purpose fair does not exist in the
tech file"). I am using HCMOS8D (0.18u tech) from ST microelectronics.
When I try to extract the layout I get the following error.

"Errors exist in the rules file
"/sw/cadence/libraries/HCMOS8D//DK_hcmos8d_4.0/Opus/DK_hcmos8d/divaEXT.rul".

Could you please throw some light on where the problem could be.

Thanks and Regards,
Kamesh.

The message is telling you that the rules are trying to create data on a
layer purpose pair that has not been defined. Quite often this is for a
saveInterconnect command where you have poly/drawing but not poly/net.
It is likely to be some other layer than poly, but you get the idea, and
the message should be telling you which layer purpose pair is missing.
Simply edit the layers to have that layer purpose pair defined.

 

[Andrew Beckett]

On Wed, 18 Oct 2006 21:12:49 -0700, Edward Kalenda <diva@cadence.com> wrote:

On 18 Oct 2006 05:54:49 -0700, "kamesh" <vkamesh@gmail.com> wrote:

Dear all,

I am using cadence 5.0.33 and DRC runs fine without any errors (but
there are some warnings like "layer purpose fair does not exist in the
tech file"). I am using HCMOS8D (0.18u tech) from ST microelectronics.
When I try to extract the layout I get the following error.

"Errors exist in the rules file
"/sw/cadence/libraries/HCMOS8D//DK_hcmos8d_4.0/Opus/DK_hcmos8d/divaEXT.rul".

Could you please throw some light on where the problem could be.

Thanks and Regards,
Kamesh.

The message is telling you that the rules are trying to create data on a
layer purpose pair that has not been defined. Quite often this is for a
saveInterconnect command where you have poly/drawing but not poly/net.
It is likely to be some other layer than poly, but you get the idea, and
the message should be telling you which layer purpose pair is missing.
Simply edit the layers to have that layer purpose pair defined.

This question was also posted on one of the cdnusers.org forums:

http://www.cdnusers.org/Forums/tabid/52/forumid/61/postid/2440/view/topic/Default.aspx

Rather than replying with the same information here, take a look at the posting
link above - I'd encourage other comp.cad.cadence users to monitor the cdnusers
forums too, and respond to questions there...

Regards,

Andrew.
--
Andrew Beckett
Principal European Technology Leader
Cadence Design Systems, UK.

 

[Bernd Fischer]

This question was also posted on one of the cdnusers.org forums:

http://www.cdnusers.org/Forums/tabid/52/forumid/61/postid/2440/view/topic/Default.aspx

Rather than replying with the same information here, take a look at the posting
link above - I'd encourage other comp.cad.cadence users to monitor the cdnusers
forums too, and respond to questions there...

And also on
http://www.designers-guide.org/Forum/YaBB.pl?num=1161173987

Bernd