Error "Unsupported Clock Statement" when asigning a value to

[Georg Gläser]

Hi there!
I've written a piece of VHDL-code in Xilinx ISE 8.1 WebPack, that should
hold an output high for 330 ns (clock 18MHz). I get an error that i have an
unsupported Clock statement in my code in a line where I'm only trying to
assign a value to a signal. Can you help me?

Here is my code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity lphold is
Port ( clk : in STD_LOGIC;
set : in STD_LOGIC;
lp : out STD_LOGIC);
end lphold;

architecture Behavioral of lphold is
signal count: std_logic_vector(0 to 1):="00";
signal lp_tmp: std_logic := '0';
begin
process(clk, set)
begin
if (set = '1') then
lp_tmp <= '1';
elsif (rising_edge(clk) and set = '1') then
count <= count + 1;
if (count = "10") then
count <= "00";
end if;
elsif (count = "00") then
lp_tmp <= '0';
end if;
end process;
lp <= lp_tmp;


Many Thx for each answer!
Georg


end Behavioral;

 

[Georg Gläser]

I forgot sth. . . . the error occurs on "lp_tmp <= '1';"
I still don't know why . . .

 

[Peter]

architecture Behavioral of lphold is
signal count: std_logic_vector(0 to 1):="00";
signal lp_tmp: std_logic := '0';
begin
process(clk, set)
begin
if (set = '1') then
lp_tmp <= '1';
elsif (rising_edge(clk) and set = '1') then
count <= count + 1;
if (count = "10") then
count <= "00";
end if;
elsif (count = "00") then
lp_tmp <= '0';
end if;
end process;
lp <= lp_tmp;

Hi,

There are some strange things in your code:

If set = '1' -- Asynchronous set has highest priority
Elsif rising_edge(clk) AND set = '1' -- Gated clock with asynchronous
set??
--
--
Elsif (count ="00") ... -- To be executed in absence of
-- asynchronous set or
-- rising edge of clock??

These kind of problems may be avoided if you use a
synchronous template:

Process(clk,reset)
Begin
if reset='1' then
-- Initialize all signals
elsif rising_edge(clk) then
if something then
---
elsif something_else then
---
end if
--
end if;
-- Nothing more here!
End process;

Everything after the "elsif rising_edge" will generate synchronous
logic.
The only asychronous part is the initialization of all signals.

Regards, Peter