Error :Nonresolved signal 'out1' has multiple sources.

[priya]

Hi all,

I am pasting Vhdl Code for AND GATE ..I got the below error while
compiling this VHDL code...


** Error: foreign.vhd(46): Nonresolved signal 'out1' has multiple
sources.



In my VHDl Code I have to send the And_gate module output to the input
of out_gate Module. Here I am getting this error...How to pass the
first output to the input of second module? is there anyway to pass
this ?


What is problem in my code?

library ieee; use ieee.std_logic_1164.all;

entity out_gate is
port ( out1: inout bit;
out2 : out bit
);
end out_gate;

architecture only1 of out_gate is

begin

end;


entity and_gate is
port ( in1, in2 : in bit;
out1 : inout bit
);
end and_gate;

architecture only of and_gate is


begin
out1<=in1 and in2;
end;



entity and4 is

port ( in1, in2 : in bit;
out1 : inout bit;
out2: out bit
);
end;

architecture only of and4 is

component and_gate
port ( in1, in2 : in bit; out1 : inout bit );
end component;
component out_gate
port (out1: inout bit; out2 : out bit );
end component;



begin

u: and_gate port map( in1, in2,out1);
r: out_gate port map(out2,out1);
end;

-- -- --

entity testbench is
end testbench;

architecture a of testbench is

component and4
port ( in1, in2 : in bit;
out1 : inout bit;
out2ut bit);
end component;


signal bv1 : bit;
signal bv2 : bit;
signal bv3 : bit;
signal bv4 : bit;

begin

t1 : and4
port map ( bv1, bv2, bv3,bv4 );

end a;

regards,
priya

 

[Hubble]

You should not use an inout port and declare a signal inside
architecture only of and4 to pass the data:

Replace all inout definitions with out.

architecture only of and4 is


component and_gate
port ( in1, in2 : in bit; out1 : inout bit );
end component;
component out_gate
port (out1: inout bit; out2 : out bit );
end component;


signal out1data: bit;
begin
out1<=out1data;

u: and_gate port map( in1, in2,out1data);
r: out_gate port map(out1data,out2);
end;

HTH

Hubble

 

[Duane Clark]

priya wrote:

Hi all,

I am pasting Vhdl Code for AND GATE ..I got the below error while
compiling this VHDL code...


** Error: foreign.vhd(46): Nonresolved signal 'out1' has multiple
sources.

The error message is telling you exactly what the problem is. You need
to study up on resolution functions, and you will then understand what
the problem is and how to fix it.