ERROR MESSAGE IN MODELSIM

[Amit]

HELLO GROUP,

IN THE FOLLOWING BLOCK. I'M GETTING ERROR AS:
** Error: arbit.vhd(39): Case statement covers only 1 out of 5 cases.
<<<<< ERROR
** Error: arbit.vhd(18): Nonresolved signal 'state_reg' has multiple
sources. <<<< ERROR



architecture arbiter_discipline_arch of Arbiter is

type arbit_state_type is (init, grant0, grant1, grant2, grant3);
signal state_reg, state_next : arbit_state_type; <<<<<<<<<<<<<<<<<<
LINE 18

begin

--state register
process(clock, reset)
begin

if (reset = '1') then
state_reg <= init;
elsif(clock'event and clock = '1' ) then
state_reg <= state_next;
end if;

end process;

process(state_reg, acknowledge, request)
begin

acknowledge <= "0000";

case state_reg is <<<<<<<<<<<<<<<<<< LINE 39

when init =>
if request(0) = '1' then
state_reg <= grant0;
else
state_reg <= init;
end if;


end case;
end process;

THANKS,

 

[Amit]

On Jun 8, 4:36 pm, Amit <amit.ko...@gmail.com> wrote:

HELLO GROUP,

IN THE FOLLOWING BLOCK. I'M GETTING ERROR AS:
** Error: arbit.vhd(39): Case statement covers only 1 out of 5 cases.
ERROR
** Error: arbit.vhd(18): Nonresolved signal 'state_reg' has multiple
sources. <<<< ERROR

architecture arbiter_discipline_arch of Arbiter is

type arbit_state_type is (init, grant0, grant1, grant2, grant3);
signal state_reg, state_next : arbit_state_type;
LINE 18

begin

--state register
process(clock, reset)
begin

if (reset = '1') then
state_reg <= init;
elsif(clock'event and clock = '1' ) then
state_reg <= state_next;
end if;

end process;

process(state_reg, acknowledge, request)
begin

acknowledge <= "0000";

case state_reg is <<<<<<<<<<<<<<<<<< LINE 39

when init =
if request(0) = '1' then
state_reg <= grant0;
else
state_reg <= init;
end if;

end case;
end process;

THANKS,

solved. thanks anyway.