ERROR:MapLib:30 - LOC constraint P11 on vga_b_out<1> is inva

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Dear all first of all want thanx to everyone who belong to this forum and give help to each other.

I use Xilinx ISE 14.7, and ML405

I checked ML405's schematic that pins, and are exist,i used advise of Aurelian Lazarut (cleaning project files) but no success. It cannot be mapped.

Could someone help me with this problem?

Here is Errors.

ERROR:MapLib:30 - LOC constraint M19 on SW1 is invalid: No such site on the
device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'.
ERROR:MapLib:30 - LOC constraint P16 on SW2 is invalid: No such site on the
device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'.
ERROR:MapLib:30 - LOC constraint M11 on SW3 is invalid: No such site on the
device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'.
ERROR:MapLib:30 - LOC constraint N11 on SW4 is invalid: No such site on the
device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'.
ERROR:MapLib:30 - LOC constraint M10 on SW5 is invalid: No such site on the
device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'.
ERROR:MapLib:30 - LOC constraint M9 on SW6 is invalid: No such site on the
device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'.
ERROR:MapLib:30 - LOC constraint N8 on SW7 is invalid: No such site on the
device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'.
ERROR:MapLib:30 - LOC constraint N7 on SW8 is invalid: No such site on the
device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'.
ERROR:MapLib:30 - LOC constraint P10 on vga_b_out&lt;0&gt; is invalid: No such site on
the device. To bypass this error set the environment variable
'XIL_MAP_LOCWARN'.
ERROR:MapLib:30 - LOC constraint P11 on vga_b_out&lt;1&gt; is invalid: No such site on
the device. To bypass this error set the environment variable
'XIL_MAP_LOCWARN'.
ERROR:MapLib:30 - LOC constraint R8 on vga_b_out&lt;2&gt; is invalid: No such site on
the device. To bypass this error set the environment variable
'XIL_MAP_LOCWARN'.
ERROR:MapLib:30 - LOC constraint N9 on vga_g_out&lt;0&gt; is invalid: No such site on
the device. To bypass this error set the environment variable
'XIL_MAP_LOCWARN'.
ERROR:MapLib:30 - LOC constraint N6 on vga_g_out&lt;1&gt; is invalid: No such site on
the device. To bypass this error set the environment variable
'XIL_MAP_LOCWARN'.
ERROR:MapLib:30 - LOC constraint P6 on vga_g_out&lt;2&gt; is invalid: No such site on
the device. To bypass this error set the environment variable
'XIL_MAP_LOCWARN'.
ERROR:MapLib:30 - LOC constraint R6 on vga_r_out&lt;0&gt; is invalid: No such site on
the device. To bypass this error set the environment variable
'XIL_MAP_LOCWARN'.
ERROR:MapLib:30 - LOC constraint R7 on vga_r_out&lt;1&gt; is invalid: No such site on
the device. To bypass this error set the environment variable
'XIL_MAP_LOCWARN'.
ERROR:MapLib:30 - LOC constraint P9 on vga_r_out&lt;2&gt; is invalid: No such site on
the device. To bypass this error set the environment variable
'XIL_MAP_LOCWARN'.
 
Looks to me as if you have the wrong package set in your project settings.

Mike
 
On Sunday, October 25, 2015 at 12:39:11 PM UTC+6, Mike Field wrote:
Looks to me as if you have the wrong package set in your project settings.

Mike
Click to expand...

There is only one package FF672 in design properties no any other, so i used it.

here is my UCF file :

NET "SW1" LOC = "M19" ;
NET "SW2" LOC = "P16" ;
NET "SW3" LOC = "M11" ;
NET "SW4" LOC = "N11" ;
NET "SW5" LOC = "M10" ;
NET "SW6" LOC = "M9" ;
NET "SW7" LOC = "N8" ;
NET "SW8" LOC = "N7" ;
NET "SW1" CLOCK_DEDICATED_ROUTE = FALSE;
NET "SW2" CLOCK_DEDICATED_ROUTE = FALSE;
NET "SW3" CLOCK_DEDICATED_ROUTE = FALSE;
NET "SW4" CLOCK_DEDICATED_ROUTE = FALSE;
NET "SW5" CLOCK_DEDICATED_ROUTE = FALSE;
NET "SW6" CLOCK_DEDICATED_ROUTE = FALSE;
NET "SW7" CLOCK_DEDICATED_ROUTE = FALSE;
NET "SW8" CLOCK_DEDICATED_ROUTE = FALSE;
NET "pushE" LOC = "m6" ;
NET "pushN" LOC = "g11" ;
NET "pushS" LOC = "l10" ;
NET "pushW" LOC = "k8" ;
####################### VGA ######################
NET "vga_b_out&lt;0&gt;" LOC = "P10" ;
NET "vga_b_out&lt;1&gt;" LOC = "P11" ;
NET "vga_b_out&lt;2&gt;" LOC = "R8" ;
NET "vga_b_out&lt;3&gt;" LOC = "f4" ;
NET "vga_b_out&lt;4&gt;" LOC = "j4" ;
NET "vga_b_out&lt;5&gt;" LOC = "g9" ;
NET "vga_b_out&lt;6&gt;" LOC = "j5" ;
NET "vga_b_out&lt;7&gt;" LOC = "h3" ;
#NET "vga_blank_n" LOC = "M24" ;
NET "vga_clk_out" LOC = "AC7" ;
NET "vga_g_out&lt;0&gt;" LOC = "N9" ;
NET "vga_g_out&lt;1&gt;" LOC = "N6" ;
NET "vga_g_out&lt;2&gt;" LOC = "p6" ;
NET "vga_g_out&lt;3&gt;" LOC = "j3" ;
NET "vga_g_out&lt;4&gt;" LOC = "k7" ;
NET "vga_g_out&lt;5&gt;" LOC = "k3" ;
NET "vga_g_out&lt;6&gt;" LOC = "g10" ;
NET "vga_g_out&lt;7&gt;" LOC = "k6" ;
NET "VGA_HSYNC" LOC = "C3" ;
#NET "vga_psave_n" LOC = "M25" ;
NET "vga_r_out&lt;0&gt;" LOC = "R6" ;
NET "vga_r_out&lt;1&gt;" LOC = "R7" ;
NET "vga_r_out&lt;2&gt;" LOC = "P9" ;
NET "vga_r_out&lt;3&gt;" LOC = "f3" ;
NET "vga_r_out&lt;4&gt;" LOC = "h7" ;
NET "vga_r_out&lt;5&gt;" LOC = "e3" ;
NET "vga_r_out&lt;6&gt;" LOC = "g5" ;
NET "vga_r_out&lt;7&gt;" LOC = "g10" ;
#NET "vga_sync_n" LOC = "L23" ;
NET "VGA_VSYNC" LOC = "d4" ;
########### CAMERA ###########
NET "camRST_i" LOC = "w23";# | CLOCK_DEDICATED_ROUTE = FALSE; #36
NET "camFRAMEVALID" LOC = "v24";# | CLOCK_DEDICATED_ROUTE = FALSE; #38
NET "camLINEVALID" LOC = "y23";# | CLOCK_DEDICATED_ROUTE = FALSE; #40
NET "camPIXCLK" LOC = "ad20" |CLOCK_DEDICATED_ROUTE = FALSE; #42
NET "camDATA&lt;4&gt;" LOC = "ad21" ;# | CLOCK_DEDICATED_ROUTE = FALSE; #44
NET "camDATA&lt;5&gt;" LOC = "ac21" ;# | CLOCK_DEDICATED_ROUTE = FALSE; #46
NET "camDATA&lt;6&gt;" LOC = "ad19" ;# | CLOCK_DEDICATED_ROUTE = FALSE; #48
NET "camDATA&lt;7&gt;" LOC = "y17";# | CLOCK_DEDICATED_ROUTE = FALSE; #50
NET "camDATA&lt;8&gt;" LOC = "ad18";# | CLOCK_DEDICATED_ROUTE = FALSE; #52
NET "camDATA&lt;9&gt;" LOC = "aa17" ;# | CLOCK_DEDICATED_ROUTE = FALSE; #54
NET "camDATA&lt;10&gt;" LOC = "ac17" ;# | CLOCK_DEDICATED_ROUTE = FALSE; #56
NET "camDATA&lt;11&gt;" LOC = "ab17";# | CLOCK_DEDICATED_ROUTE = FALSE; #58
NET "camEXPOSURE" LOC = "ab16";# | CLOCK_DEDICATED_ROUTE = FALSE; #60
NET "camOE" LOC = "ab15";# | CLOCK_DEDICATED_ROUTE = FALSE; #62
NET "camCLKIN" LOC = "aa15";# | CLOCK_DEDICATED_ROUTE = FALSE; #64
NET "camDATA&lt;4&gt;" IOSTANDARD = "LVCMOS33";
NET "camDATA&lt;5&gt;" IOSTANDARD = "LVCMOS33";
NET "camDATA&lt;6&gt;" IOSTANDARD = "LVCMOS33";
NET "camDATA&lt;7&gt;" IOSTANDARD = "LVCMOS33";
NET "camDATA&lt;8&gt;" IOSTANDARD = "LVCMOS33";
NET "camDATA&lt;9&gt;" IOSTANDARD = "LVCMOS33";
NET "camDATA&lt;10&gt;" IOSTANDARD = "LVCMOS33";
NET "camDATA&lt;11&gt;" IOSTANDARD = "LVCMOS33";
NET "camEXPOSURE" IOSTANDARD = "LVCMOS33";
NET "camFRAMEVALID" IOSTANDARD = "LVCMOS33";
NET "camLINEVALID" IOSTANDARD = "LVCMOS33";
NET "camRST_i" IOSTANDARD = "LVCMOS33";
NET "camOE" IOSTANDARD = "LVCMOS33";
NET "camPIXCLK" IOSTANDARD = "LVCMOS33";
NET "camCLKIN" IOSTANDARD = "LVCMOS33";
 
On Sunday, October 25, 2015 at 1:25:15 PM UTC+6, abi...@gmail.com wrote:
On Sunday, October 25, 2015 at 12:39:11 PM UTC+6, Mike Field wrote:
Looks to me as if you have the wrong package set in your project settings.

Mike

There is only one package FF672 in design properties no any other, so i used it.

here is my UCF file :

NET "SW1" LOC = "M19" ;
NET "SW2" LOC = "P16" ;
NET "SW3" LOC = "M11" ;
Click to expand...

Partially solved. used link http://www.edaboard.com/thread11331.html

But appear next error :

ERROR:pack:2811 - Directed packing was unable to obey the user design
constraints (LOC=G10) which requires the combination of the symbols listed
below to be packed into a single IOB component.
 
On Sunday, October 25, 2015 at 3:05:09 PM UTC+6, abi...@gmail.com wrote:
On Sunday, October 25, 2015 at 1:25:15 PM UTC+6, abi...@gmail.com wrote:
On Sunday, October 25, 2015 at 12:39:11 PM UTC+6, Mike Field wrote:
Looks to me as if you have the wrong package set in your project settings.

Mike

There is only one package FF672 in design properties no any other, so i used it.

here is my UCF file :

NET "SW1" LOC = "M19" ;
NET "SW2" LOC = "P16" ;
NET "SW3" LOC = "M11" ;

Partially solved. used link http://www.edaboard.com/thread11331.html

But appear next error :

ERROR:pack:2811 - Directed packing was unable to obey the user design
constraints (LOC=G10) which requires the combination of the symbols listed
below to be packed into a single IOB component.
Click to expand...

Solved http://www.xilinx.com/support/answers/36343.html
 
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