Error in the assign statement

[kb33]

Hi,

If I write an ASSIGN statement in the following manner, Modelsim
complains that there is an illegal left-handed side in the continuous
assignment and it doesn't compile the code:

input [2:0] inp_a, inp_b;
wire [2:0] array_a [0:7];
wire [2:0] array_b [0:3];
wire [2:0] array_c [0:3];
genvar i;

generate
for (i=0; i<4; i=i+1)
begin : test_blk
assign array_a [array_b ] = (condition == `SATISFIED) ?
inp_a : 0;
assign array_a [array_c ] = (condition == `SATISFIED) ?
inp_b : 0;
end
endgenerate

As an example, we can assume that array_b has the values 0,2,4,6 and
array_c has the values 1,3,5,7. Hence, if the conditions are met, the
following values should hold good:
array_a [0] = inp_a;
array_a [1] = inp_b;
array_a [2] = inp_a;
array_a [3] = inp_b;
array_a [4] = inp_a;
array_a [5] = inp_b;
array_a [6] = inp_a;
array_a [7] = inp_b;

So what is a good way to assign values (without using an ALWAYS
block) ?

kb33

 

[Kevin Neilson]

kb33 wrote:

Hi,

If I write an ASSIGN statement in the following manner, Modelsim
complains that there is an illegal left-handed side in the continuous
assignment and it doesn't compile the code:

input [2:0] inp_a, inp_b;
wire [2:0] array_a [0:7];
wire [2:0] array_b [0:3];
wire [2:0] array_c [0:3];
genvar i;

generate
for (i=0; i<4; i=i+1)
begin : test_blk
assign array_a [array_b ] = (condition == `SATISFIED) ?
inp_a : 0;
assign array_a [array_c ] = (condition == `SATISFIED) ?
inp_b : 0;
end
endgenerate

As an example, we can assume that array_b has the values 0,2,4,6 and
array_c has the values 1,3,5,7. Hence, if the conditions are met, the
following values should hold good:
array_a [0] = inp_a;
array_a [1] = inp_b;
array_a [2] = inp_a;
array_a [3] = inp_b;
array_a [4] = inp_a;
array_a [5] = inp_b;
array_a [6] = inp_a;
array_a [7] = inp_b;

So what is a good way to assign values (without using an ALWAYS
block) ?

kb33
This might work if array_b and array_c are parameters instead of wires.

This means they would be constants, but I'll make the assumption that
that's what you want. Unfortunately you can't have a 2D parameter
array, but you can flatten the array in this manner:

parameter [3*7-1:0] array_a = {3'd7, 3'd5, 3'd3, 3'd1};
generate
for (i=0; i<4; i=i+1)
begin : test_blk
assign array_a [array_b[3*i+:3]] = (condition == `SATISFIED)
? inp_a : 0;
....

-Kevin

 

[Kevin Neilson]

Kevin Neilson wrote:

kb33 wrote:
Hi,

If I write an ASSIGN statement in the following manner, Modelsim
complains that there is an illegal left-handed side in the continuous
assignment and it doesn't compile the code:

input [2:0] inp_a, inp_b;
wire [2:0] array_a [0:7];
wire [2:0] array_b [0:3];
wire [2:0] array_c [0:3];
genvar i;

generate
for (i=0; i<4; i=i+1)
begin : test_blk
assign array_a [array_b ] = (condition == `SATISFIED) ?
inp_a : 0;
assign array_a [array_c ] = (condition == `SATISFIED) ?
inp_b : 0;
end
endgenerate

As an example, we can assume that array_b has the values 0,2,4,6 and
array_c has the values 1,3,5,7. Hence, if the conditions are met, the
following values should hold good:
array_a [0] = inp_a;
array_a [1] = inp_b;
array_a [2] = inp_a;
array_a [3] = inp_b;
array_a [4] = inp_a;
array_a [5] = inp_b;
array_a [6] = inp_a;
array_a [7] = inp_b;

So what is a good way to assign values (without using an ALWAYS
block) ?

kb33
This might work if array_b and array_c are parameters instead of wires.
This means they would be constants, but I'll make the assumption that
that's what you want. Unfortunately you can't have a 2D parameter
array, but you can flatten the array in this manner:

parameter [3*7-1:0] array_a = {3'd7, 3'd5, 3'd3, 3'd1};
generate
for (i=0; i<4; i=i+1)
begin : test_blk
assign array_a [array_b[3*i+:3]] = (condition == `SATISFIED) ?
inp_a : 0;
...

-Kevin
You might also be able to rearrange the parameter so you don't have to

assign the elements "backwards":
parameter [0:3*7-1] array_a = {3'd1, 3'd3, 3'd5, 3'd7};

 

On Apr 7, 2:28 pm, kb33 <kanchan.devarako...@gmail.com> wrote:

If I write an ASSIGN statement in the following manner, Modelsim
complains that there is an illegal left-handed side in the continuous
assignment and it doesn't compile the code:

          assign array_a [array_b ] = (condition == `SATISFIED) ?
inp_a : 0;

You cannot use a non-constant value (array_b) to control which net is
being driven by a continuous assignment. That would be like the
driver getting re-wired to a different net every time array_b changes
value, after the chip has already been constructed.

You need to view this from the opposite direction. You cannot think
about it as "What output should this particular input be driven
onto?" You have to think about it as "What input should drive this
particular output?" Each continuous assignment is logic hardwired to
drive a particular net as its left-hand side. You have to design the
right logic on the right-hand side to compute the correct value (such
as a multiplexer selecting from a variety of input values).