error in Synopsys Design Compiler

[Tiberiu Chelcea]

Hey,

I get this strange error message in Synopsys Design Compiler when trying
to elaborate a design:

Error: Width of port p9 is inconsistent with other instances in routine
size. (ELAB-369)

I don't really know how to correct the problem, since SDC is not even
saying on which line, or which module, or which input causes the problem.
Could not find anything about this "ELAB-369" error message in SDC's
documentation.

Any help/pointer would be really appreciated.

Thank you.

 

[David Jones]

In article <Pine.LNX.4.33L.0402042331230.7221-100000@ux6.sp.cs.cmu.edu>,
Tiberiu Chelcea <tibi@cs.cmu.edu> wrote:

Hey,

I get this strange error message in Synopsys Design Compiler when trying
to elaborate a design:

Error: Width of port p9 is inconsistent with other instances in routine
size. (ELAB-369)

I don't really know how to correct the problem, since SDC is not even
saying on which line, or which module, or which input causes the problem.
Could not find anything about this "ELAB-369" error message in SDC's
documentation.

Well, you DO know that port "p9" is involved somehow.

How many instances of port "p9" do you have in your design?

If there are too many to look at, then rename them to "p9_a", "p9_b"
and so on, resimulate to make sure your design has not broken, then
resynthesize.

 

[Tiberiu Chelcea]

Well, you DO know that port "p9" is involved somehow.

How many instances of port "p9" do you have in your design?

If there are too many to look at, then rename them to "p9_a", "p9_b"
and so on, resimulate to make sure your design has not broken, then
resynthesize.
Thank you for the suggestion. Unfortunatelly, I don't have *any* port p9

whatsoever in any of the submodules or top module, which makes it even
more cryptic.

A few days ago, I got this error for a different design. Basically,
imagine, say, an OR gate (tech-mapped) with one of the inputs constant
0. I'd write:
OR I0 (Z, A, 0);
and the error would appear (different pX - can't remember which).

My hack was to declare a "logic0" gate
module logic0 (out);
output out;
assign out = 1'b0;
endmodule

and then the OR expression would be rewritten
wire gnd;
logic0 l0 (gnd);
OR I0 (Z, A, gnd);

This eliminated the error. However, for this design, there is no module
which has constant 0/1/whatever inputs, and I still get the error. It's
not that one input to a module is not the correct size, that's detected by
SDC. So, I'm afraid that with the above hack I've just been lucky for some
particular case, but not identified the actual problem. And the problem is
likely to repeat, since the Verilog code is generated automatically by
a compiler we're working on.

I'm using Design Compiler "Version 2002.05-SP2 for sparcOS5 -- Nov 15,
2002", if that is of any help.

Thank you.
Tibi