Error in Clock Divider!

S

Santosh

Guest
I have got a clock divider code as follows:

entity divClk8 is
Port ( CLK : in std_logic;
CLK_OUT : out std_logic);
end divClk8;

architecture Behavioral of divClk8 is
signal count : std_logic_vector (3 downto 0) := "1111";
signal reset : std_logic := '0';

begin
process(CLK)
begin
if(reset = '1') then
count <= "0000";
elsif(rising_edge(CLK)) then
count <= count + 1;
end if;
end process;
CLK_OUT <= count(3);
reset <= (count(3) and not(count(2))and not(count(1))and
not(count(0)));
end Behavioral;



But when I try to compile it using ModelSim I get the following error

-- No feasible entries for infix operator "+". Type error resolving
infix expression "+" as type ieee.std_logic_1164.std_logic_vector.



I didn't get what the error message says. A little word of advice
would be really helpful!

Regards
San
 
Check your used libraries. Modelsim don't find an implementation
to add an integer 1 to a std_logic_vector.

On Wed, 2010-12-29 at 07:43 -0800, Santosh wrote:
I have got a clock divider code as follows:

entity divClk8 is
Port ( CLK : in std_logic;
CLK_OUT : out std_logic);
end divClk8;

architecture Behavioral of divClk8 is
signal count : std_logic_vector (3 downto 0) := "1111";
signal reset : std_logic := '0';

begin
process(CLK)
begin
if(reset = '1') then
count <= "0000";
elsif(rising_edge(CLK)) then
count <= count + 1;
end if;
end process;
CLK_OUT <= count(3);
reset <= (count(3) and not(count(2))and not(count(1))and
not(count(0)));
end Behavioral;



But when I try to compile it using ModelSim I get the following error

-- No feasible entries for infix operator "+". Type error resolving
infix expression "+" as type ieee.std_logic_1164.std_logic_vector.



I didn't get what the error message says. A little word of advice
would be really helpful!

Regards
San
Click to expand...
 
On Dec 29, 10:43 am, Santosh <santos...@gmail.com> wrote:
I have got a clock divider code as follows:

architecture Behavioral of divClk8 is
signal count : std_logic_vector (3 downto 0) := "1111";
signal reset : std_logic := '0';

begin
process(CLK)
begin
if(reset = '1') then
count <= "0000";
elsif(rising_edge(CLK)) then
count <= count + 1;


But when I try to compile it using ModelSim I get the following error

--  No feasible entries for infix operator "+". Type error resolving
infix expression "+" as type ieee.std_logic_1164.std_logic_vector.
Click to expand...
std_logic_vector signals do not have any math operators defined for
them. A std_logic_vector is just a collection of bits with no numeric
interpretation. To do what you want, you need to use a signal of type
unsigned which is defined in the package 'ieee.numeric_std'. To fix
up the code:

- Add the line "use ieee.numeric_std.all" right after the line where
you currently have "library ieee"
- Change "signal count : std_logic_vector (3 downto 0)" to "signal
count : unsigned (3 downto 0)"

Kevin Jennings
 
On Dec 29, 8:43 am, Santosh <santos...@gmail.com> wrote:
I have got a clock divider code as follows:

entity divClk8 is
   Port ( CLK : in std_logic;
          CLK_OUT : out std_logic);
end divClk8;

architecture Behavioral of divClk8 is
signal count : std_logic_vector (3 downto 0) := "1111";
signal reset : std_logic := '0';

begin
process(CLK)
begin
if(reset = '1') then
count <= "0000";
elsif(rising_edge(CLK)) then
count <= count + 1;
end if;
end process;
CLK_OUT <= count(3);
reset <= (count(3) and not(count(2))and not(count(1))and
not(count(0)));
end Behavioral;

But when I try to compile it using ModelSim I get the following error

--  No feasible entries for infix operator "+". Type error resolving
infix expression "+" as type ieee.std_logic_1164.std_logic_vector.

I didn't get what the error message says. A little word of advice
would be really helpful!

Regards
San
Click to expand...
In addition to the responses you've had so far, don't you need to
include the port for the reset line input and also include it in your
process sensitivity list?
 
Le 29/12/2010 16:43, Santosh a écrit :
I have got a clock divider code as follows:

entity divClk8 is
Port ( CLK : in std_logic;
CLK_OUT : out std_logic);
end divClk8;

architecture Behavioral of divClk8 is
signal count : std_logic_vector (3 downto 0) := "1111";
signal reset : std_logic := '0';

begin
process(CLK)
begin
if(reset = '1') then
count<= "0000";
elsif(rising_edge(CLK)) then
count<= count + 1;
end if;
end process;
CLK_OUT<= count(3);
reset<= (count(3) and not(count(2))and not(count(1))and
not(count(0)));
end Behavioral;



But when I try to compile it using ModelSim I get the following error

-- No feasible entries for infix operator "+". Type error resolving
infix expression "+" as type ieee.std_logic_1164.std_logic_vector.
Click to expand...
What do you plan to do with your divided clock output ? It will be a
short glith-like pulse that will be very dependent on many things
(mainly temperature) that won't be very usable.

Nicolas
 
Overloading will allow you to add integers like 1 (such as for basic
counters) to your std_logic_vector's. One of the IEEE libraries will
allow you to do this if you include the right one. Don't remember
which one off top of my head.

Some other observations:
- You are missing a reset input.
- You don't need to include reset into sensitivity list if you are
treating it synchronously.
- If you maintain std_logic_vector(3 downto 0) type OR use integer of
"range 0 to 3" there is no need to reset counter if you intend to
rollover at max (all 1's) value.

John
 
"Santosh" <santos2k7@gmail.com> wrote in message
news:17ff8d8d-0fa9-41d3-8946-53879f254399@r8g2000prm.googlegroups.com...
I have got a clock divider code as follows:

entity divClk8 is
Port ( CLK : in std_logic;
CLK_OUT : out std_logic);
end divClk8;

architecture Behavioral of divClk8 is
signal count : std_logic_vector (3 downto 0) := "1111";
signal reset : std_logic := '0';

begin
process(CLK)
begin
if(reset = '1') then
count <= "0000";
elsif(rising_edge(CLK)) then
count <= count + 1;
end if;
end process;
CLK_OUT <= count(3);
reset <= (count(3) and not(count(2))and not(count(1))and
not(count(0)));
end Behavioral;



But when I try to compile it using ModelSim I get the following error

-- No feasible entries for infix operator "+". Type error resolving
infix expression "+" as type ieee.std_logic_1164.std_logic_vector.
Click to expand...
Lots of potential issues with this code, but try:
count <= count + "1"; -- now with quotes on the 1
 
On 29 Dez. 2010, 17:32, Dave <starfire...@cableone.net> wrote:

In addition to the responses you've had so far, don't you need to
include the port for the reset line input and also include it in your
process sensitivity list?
Click to expand...
No as this seems to be a synchronous reset which is internal
generated.
 
On 29 Dez. 2010, 19:22, Nicolas Matringe <nicolas.matri...@fre.fre>
wrote:
Le 29/12/2010 16:43, Santosh a crit :



I have got a clock divider code as follows:

entity divClk8 is
    Port ( CLK : in std_logic;
           CLK_OUT : out std_logic);
end divClk8;

architecture Behavioral of divClk8 is
signal count : std_logic_vector (3 downto 0) := "1111";
signal reset : std_logic := '0';

begin
process(CLK)
begin
if(reset = '1') then
count<= "0000";
elsif(rising_edge(CLK)) then
count<= count + 1;
end if;
end process;
CLK_OUT<= count(3);
reset<= (count(3) and not(count(2))and not(count(1))and
not(count(0)));
end Behavioral;

But when I try to compile it using ModelSim I get the following error

--  No feasible entries for infix operator "+". Type error resolving
infix expression "+" as type ieee.std_logic_1164.std_logic_vector.

What do you plan to do with your divided clock output ? It will be a
short glith-like pulse that will be very dependent on many things
(mainly temperature) that won't be very usable.
Click to expand...
Please explain your problems with the functional code?
I would have written it a bit shorter, but can't see a problem in
generating a divided clock with 8 cycles '0' and 8 cycles '1'

bye Thomas
 
On Jan 3, 9:08 am, Thomas Stanka <usenet_nospam_va...@stanka-web.de>
wrote:
On 29 Dez. 2010, 17:32, Dave <starfire...@cableone.net> wrote:

In addition to the responses you've had so far, don't you need to
include the port for the reset line input and also include it in your
process sensitivity list?

No as this seems to be a synchronous reset which is internal
generated.
Click to expand...
You might want to take another look. The OP coded an asynchronous
reset but forgot to include the reset signal in the sensitivity list.

KJ
 
On Jan 3, 9:45 am, "Morten Leikvoll" <mleik...@yahoo.nospam> wrote:
--  No feasible entries for infix operator "+". Type error resolving
infix expression "+" as type ieee.std_logic_1164.std_logic_vector.

Lots of potential issues with this code, but try:
count <= count + "1"; -- now with quotes on the 1
Click to expand...
You might want to try your suggestion first, you'll get the exact same
error message. You might also want to read my first post which has
the solution.

KJ
 
At least I can do addition of std_logic_vectors with no special settings in
Quartus 10.
But for integers, you need the numeric library.
The code below is some tested and implemented code I found on my drive.
-------------
architecture rtl of test is

signal testcnt : std_logic_vector(29 downto 0);
constant testval : std_logic_vector(29 downto
0):=(testcnt'high=>'1',0=>'1',others =>'0');

begin
process(clk,rst) begin
if(rising_edge(clk)) then
test<='0';
testcnt<=testcnt+"1";
if(rst='1' or testcnt>testval) then
testcnt<=(others=>'0');
test<='1';
end if;
end if;
end process;
end rtl;



"KJ" <kkjennings@sbcglobal.net> wrote in message
news:24672c6f-e84e-4475-b5c1-eb3835883b5a@j25g2000vbs.googlegroups.com...
On Jan 3, 9:45 am, "Morten Leikvoll" <mleik...@yahoo.nospam> wrote:
-- No feasible entries for infix operator "+". Type error resolving
infix expression "+" as type ieee.std_logic_1164.std_logic_vector.

Lots of potential issues with this code, but try:
count <= count + "1"; -- now with quotes on the 1
Click to expand...
You might want to try your suggestion first, you'll get the exact same
error message. You might also want to read my first post which has
the solution.

KJ
 
"KJ" <kkjennings@sbcglobal.net> wrote in message
news:16d20dfa-e437-44ce-992a-7fce6b4d4bc5@l8g2000yqh.googlegroups.com...
On Dec 29, 10:43 am, Santosh <santos...@gmail.com> wrote:
I have got a clock divider code as follows:

architecture Behavioral of divClk8 is
signal count : std_logic_vector (3 downto 0) := "1111";
signal reset : std_logic := '0';

begin
process(CLK)
begin
if(reset = '1') then
count <= "0000";
elsif(rising_edge(CLK)) then
count <= count + 1;


But when I try to compile it using ModelSim I get the following error

-- No feasible entries for infix operator "+". Type error resolving
infix expression "+" as type ieee.std_logic_1164.std_logic_vector.


std_logic_vector signals do not have any math operators defined for
them. A std_logic_vector is just a collection of bits with no numeric
interpretation. To do what you want, you need to use a signal of type
unsigned which is defined in the package 'ieee.numeric_std'. To fix
up the code:

- Add the line "use ieee.numeric_std.all" right after the line where
you currently have "library ieee"
- Change "signal count : std_logic_vector (3 downto 0)" to "signal
count : unsigned (3 downto 0)"

Kevin Jennings
Click to expand...
Alternatively use VHDL2008's numeric_std_unsigned which is a replacement for the
none standard std_logic_unsigned. You can now do unsigned arithmetic (like + 1)
on std_logic_vectors without conversions.

There is also a numeric_std_signed but Modelsim 10.0 doesn't seem to support it,

Hans
www.ht-lab.com
 
Alternatively use VHDL2008's numeric_std_unsigned which is a replacement for the
none standard std_logic_unsigned. You can now do unsigned arithmetic (like + 1)
on std_logic_vectors without conversions.

There is also a numeric_std_signed but Modelsim 10.0 doesn't seem to support it,

Hanswww.ht-lab.com
Click to expand...


Yes got it
including numeric_std_unsigned.all; solves the problem. :)
 
On Jan 4, 3:08 am, "Morten Leikvoll" <mleik...@yahoo.nospam> wrote:
At least I can do addition of std_logic_vectors with no special settings in
Quartus 10.
Click to expand...
It's not 'special settings'. In order to 'add' std_logic_vectors you
need to include the ieee.std_logic_arith package. This package
however is not standard, it is also not from IEEE. The proper package
to use when you want to do math with vectors is either
ieee.numeric_std or the more recently released fixed point package
'fixed_pkg'.

But for integers, you need the numeric library.
Click to expand...
Not true. For integers, you need no package at all. Math with
integers is supported by the language definition.

The code below is some tested and implemented code I found on my drive.
Click to expand...
Not shown in your code is the statement "use ieee.std_logic_arith.all"
which, as mentioned above, is not standard...but is required in order
to use your code 'as-is'.

<snip>
The following process code also has an unneeded signal in the
sensitivity list...left as an exercise to the reader to spot.

 process(clk,rst) begin
  if(rising_edge(clk)) then
   test<='0';
   testcnt<=testcnt+"1";
   if(rst='1' or testcnt>testval) then
    testcnt<=(others=>'0');
    test<='1';
   end if;
  end if;
 end process;
end rtl;
Click to expand...
KJ
 
"KJ" <kkjennings@sbcglobal.net> wrote in message
news:8b3f8888-75d7-4af1-906d-0e992949fad8@g26g2000vbi.googlegroups.com...
On Jan 4, 3:08 am, "Morten Leikvoll" <mleik...@yahoo.nospam> wrote:
At least I can do addition of std_logic_vectors with no special settings
in
Quartus 10.
It's not 'special settings'. In order to 'add' std_logic_vectors you
need to include the ieee.std_logic_arith package. This package
however is not standard, it is also not from IEEE. The proper package
to use when you want to do math with vectors is either
ieee.numeric_std or the more recently released fixed point package
'fixed_pkg'.
Click to expand...
When I say "special settings" I meant there was no application references to
packages (if possible at all). I use the default Quartus settings.

The code below is some tested and implemented code I found on my drive.
Not shown in your code is the statement "use ieee.std_logic_arith.all"
which, as mentioned above, is not standard...but is required in order
to use your code 'as-is'.
Click to expand...
NO, ieee.std_logic_arith.all was not in my code. Did you try it?

The following process code also has an unneeded signal in the
sensitivity list...left as an exercise to the reader to spot.
Click to expand...
True, I just add 'rst' there as my own standard, in case I need to use async
reset. When not using it, I forget to remove it, and it doesn't cause any
damage, so I don't care.
 
On Jan 7, 4:07 am, "Morten Leikvoll" <mleik...@yahoo.nospam> wrote:
"KJ" <kkjenni...@sbcglobal.net> wrote in message

The following process code also has an unneeded signal in the
sensitivity list...left as an exercise to the reader to spot.

True, I just add 'rst' there as my own standard, in case I need to use async
reset. When not using it, I forget to remove it, and it doesn't cause any
damage, so I don't care.
Click to expand...
That's not strictly true. In simulation this will cause additional,
unnecessary executions of the process when RST toggles, but then I
guess that's not very often.

I wouldn't leave those in just to keep the code clean. If nothing
else, I am sure it generates warnings which help to clutter up the
compile output and hide other, more meaningful warnings.

Rick
 
On Jan 7, 4:07 am, "Morten Leikvoll" <mleik...@yahoo.nospam> wrote:

The code below is some tested and implemented code I found on my drive..
Click to expand...

NO, ieee.std_logic_arith.all was not in my code. Did you try it?
Click to expand...
Yes, I did...apparently you did not, even though you called it "tested
and implemented code I found on my drive".

Quartus 10.0 SP1 reports the following error on the statement
"testcnt<=testcnt+"1"; "
Error (10327): VHDL error at Junk.vhd(341): can't determine definition
of operator ""+"" -- found 0 possible definitions

Modelsim 6.4 reports the following (as I mentioned in the first post)
No feasible entries for infix operator "+".

But before you get those errors, you'll have to clean up another error
because you used the name 'test' as the name of the entity and as a
signal.

architecture rtl of test is
...
test<='0';

As I suggested in my first post, you might want to try out your code
first before posting.

KJ
 
Alright, I admit changing the name of the entity after pasting, cause the
original name was not related to the function.
Also, what is missing in your attempt is:
use ieee.std_logic_unsigned.all;
Which I assumed was very common and didn't include. Sorry for that.


"KJ" <kkjennings@sbcglobal.net> wrote in message
news:872e6dca-2257-432c-95b7-1fc9ab2a0b09@m37g2000vbn.googlegroups.com...
On Jan 7, 4:07 am, "Morten Leikvoll" <mleik...@yahoo.nospam> wrote:

The code below is some tested and implemented code I found on my drive.

NO, ieee.std_logic_arith.all was not in my code. Did you try it?
Click to expand...
Yes, I did...apparently you did not, even though you called it "tested
and implemented code I found on my drive".

Quartus 10.0 SP1 reports the following error on the statement
"testcnt<=testcnt+"1"; "
Error (10327): VHDL error at Junk.vhd(341): can't determine definition
of operator ""+"" -- found 0 possible definitions

Modelsim 6.4 reports the following (as I mentioned in the first post)
No feasible entries for infix operator "+".

But before you get those errors, you'll have to clean up another error
because you used the name 'test' as the name of the entity and as a
signal.

architecture rtl of test is
...
test<='0';

As I suggested in my first post, you might want to try out your code
first before posting.

KJ
 
"KJ" <kkjennings@sbcglobal.net> wrote in message
news:872e6dca-2257-432c-95b7-1fc9ab2a0b09@m37g2000vbn.googlegroups.com...
On Jan 7, 4:07 am, "Morten Leikvoll" <mleik...@yahoo.nospam> wrote:
The code below is some tested and implemented code I found on my
drive.
NO, ieee.std_logic_arith.all was not in my code. Did you try it?
Yes, I did...apparently you did not, even though you called it "tested
and implemented code I found on my drive".

Quartus 10.0 SP1 reports the following error on the statement
"testcnt<=testcnt+"1"; "
Error (10327): VHDL error at Junk.vhd(341): can't determine definition
of operator ""+"" -- found 0 possible definitions

Modelsim 6.4 reports the following (as I mentioned in the first post)
No feasible entries for infix operator "+".

But before you get those errors, you'll have to clean up another error
because you used the name 'test' as the name of the entity and as a
signal.

architecture rtl of test is
...
test<='0';

As I suggested in my first post, you might want to try out your code
first before posting.
Click to expand...

Alright, I admit changing the name of the entity after pasting, cause the
original name was not related to the function.
Also, what is missing in your attempt is:
use ieee.std_logic_unsigned.all;
Which I assumed was very common and didn't include. Sorry for that.
 
You must log in or register to reply here.

Welcome to EDABoard.com

Sponsor

Back
Top