Error Generate Statement

I

Isaac

Guest
Hi Fellows,

I am just getting used to generate statement. Do begin with 8 bit
inverter is generated using Generate Command. Now I want to connect
the out put of one inverter to the input of other invertor or you can
say to cascade the 8 inverters. I will just apply input to the first
inverter and at every clock pulse output is tranfered sequentially to
other inverter.
I have written the VHDL code below But I am getting following error.
Help would be appreciated .


ERROR ---------------------------------------------------------------------
# Error: ELAB1_0008: generate.vhd : (31, 16): Cannot read output :
"Outputs".
# Error: ELAB1_0008: generate.vhd : (32, 16): Cannot read output :
"Outputs".
# Error: ELAB1_0008: generate.vhd : (33, 16): Cannot read output :
"Outputs".
# Error: ELAB1_0008: generate.vhd : (34, 16): Cannot read output :
"Outputs".
# Error: ELAB1_0008: generate.vhd : (35, 16): Cannot read output :
"Outputs".
# Error: ELAB1_0008: generate.vhd : (36, 16): Cannot read output :
"Outputs".
# Error: ELAB1_0008: generate.vhd : (37, 16): Cannot read output :
"Outputs".

VHDL CODE ---------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity Invert_8 is
port ( Inputs :std_logic_vector (1 to 8);
clock : in std_logic ;
Outputs : out std_logic_vector (1 to 8));
end Invert_8;

Architecture Behaviour of Invert_8 is
component Inverter
port ( I1 : std_logic ;
clock : in std_logic;
O1 : out std_logic );
end component ;
signal output1 : std_logic ;
signal output2 : std_logic ;
signal output3 : std_logic ;
signal output4 : std_logic ;
signal output5 : std_logic ;
signal output6 : std_logic ;
signal output7 : std_logic ;
begin

InverterGenerated : for I in 1 to 8 generate
Inv : Inverter port map (Inputs(I),clock, Outputs(I));
end generate ;

process (clock)
begin
if (clock'EVENT and clock ='1') then
output1 <= Outputs(1);
output2 <= Outputs(2);
output3 <= Outputs(3);
output4 <= Outputs(4);
output5 <= Outputs(5);
output6 <= Outputs(6);
output7 <= Outputs(7);
end if ;
end process ;
InverterGenerated_1 : Inverter
port map (
Inputs(1),clock, Outputs(1)
);
InverterGenerated_2 : Inverter
port map (
I1 => output1,
clock => clock, O1 => Outputs(2)
);
InverterGenerated_3 : Inverter
port map (
I1 => output2,
clock => clock, O1 => Outputs(3)
);
InverterGenerated_4 : Inverter
port map (
I1 => output3,
clock => clock, O1 => Outputs(4)
);
InverterGenerated_5 : Inverter
port map (
I1 => output4,
clock => clock, O1 => Outputs(5)
);
InverterGenerated_6 : Inverter
port map (
I1 => output5,
clock => clock, O1 => Outputs(6)
);
InverterGenerated_7 : Inverter
port map (
I1 => output6,
clock => clock, O1 => Outputs(7)
);
InverterGenerated_8 : Inverter
port map (
I1 => output7,
clock => clock, O1 => Outputs(8)
);
end Behaviour;
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity Inverter is
port ( I1 : std_logic ;
clock : in std_logic;
O1 : out std_logic );
end Inverter;
Architecture Behav of Inverter is

begin
process (I1,clock)
begin
if (clock'EVENT and clock='1') then
O1 <= not (I1);
end if;
end process ;
end Behav;
 
The error messages refer to the fact that "outputs" is declared
an output of the entity invert_8, and so you can't use their values
to assign to another signal within the entity in these lines:

process (clock)
begin
if (clock'EVENT and clock ='1') then
output1 <= Outputs(1);
output2 <= Outputs(2);
output3 <= Outputs(3);
output4 <= Outputs(4);
output5 <= Outputs(5);
output6 <= Outputs(6);
output7 <= Outputs(7);
end if ;
end process ;
Click to expand...
 
In article <d9db536c.0308071105.115657b4@posting.google.com>,
smukthav@yahoo.com says...
You cannot read the output ports. There are two ways you can solve
this....make the signals on the entity "Outputs" as type inout or
create an internal signal Outputs and assign the internal signal to
the Outputs. The second approach though is tedious doesnt actually
create anymore extra logic. The first approach sometime confuses the
synthesis tool when trying to resolve in/out and may infer tri-state
logic if it cannot figure out.
Click to expand...
You can also assign the entity "outputs" as type buffer. I recommend
the internal signal method though.

--
Keith
 
You cannot read the output ports. There are two ways you can solve
this....make the signals on the entity "Outputs" as type inout or
create an internal signal Outputs and assign the internal signal to
the Outputs. The second approach though is tedious doesnt actually
create anymore extra logic. The first approach sometime confuses the
synthesis tool when trying to resolve in/out and may infer tri-state
logic if it cannot figure out.
fpga_uk@yahoo.co.uk (Isaac) wrote in message news:<889eb3fb.0308070244.cdb8e6e@posting.google.com>...
Hi Fellows,

I am just getting used to generate statement. Do begin with 8 bit
inverter is generated using Generate Command. Now I want to connect
the out put of one inverter to the input of other invertor or you can
say to cascade the 8 inverters. I will just apply input to the first
inverter and at every clock pulse output is tranfered sequentially to
other inverter.
I have written the VHDL code below But I am getting following error.
Help would be appreciated .


ERROR ---------------------------------------------------------------------
# Error: ELAB1_0008: generate.vhd : (31, 16): Cannot read output :
"Outputs".
# Error: ELAB1_0008: generate.vhd : (32, 16): Cannot read output :
"Outputs".
# Error: ELAB1_0008: generate.vhd : (33, 16): Cannot read output :
"Outputs".
# Error: ELAB1_0008: generate.vhd : (34, 16): Cannot read output :
"Outputs".
# Error: ELAB1_0008: generate.vhd : (35, 16): Cannot read output :
"Outputs".
# Error: ELAB1_0008: generate.vhd : (36, 16): Cannot read output :
"Outputs".
# Error: ELAB1_0008: generate.vhd : (37, 16): Cannot read output :
"Outputs".

VHDL CODE ---------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity Invert_8 is
port ( Inputs :std_logic_vector (1 to 8);
clock : in std_logic ;
Outputs : out std_logic_vector (1 to 8));
end Invert_8;

Architecture Behaviour of Invert_8 is
component Inverter
port ( I1 : std_logic ;
clock : in std_logic;
O1 : out std_logic );
end component ;
signal output1 : std_logic ;
signal output2 : std_logic ;
signal output3 : std_logic ;
signal output4 : std_logic ;
signal output5 : std_logic ;
signal output6 : std_logic ;
signal output7 : std_logic ;
begin

InverterGenerated : for I in 1 to 8 generate
Inv : Inverter port map (Inputs(I),clock, Outputs(I));
end generate ;

process (clock)
begin
if (clock'EVENT and clock ='1') then
output1 <= Outputs(1);
output2 <= Outputs(2);
output3 <= Outputs(3);
output4 <= Outputs(4);
output5 <= Outputs(5);
output6 <= Outputs(6);
output7 <= Outputs(7);
end if ;
end process ;
InverterGenerated_1 : Inverter
port map (
Inputs(1),clock, Outputs(1)
);
InverterGenerated_2 : Inverter
port map (
I1 => output1,
clock => clock, O1 => Outputs(2)
);
InverterGenerated_3 : Inverter
port map (
I1 => output2,
clock => clock, O1 => Outputs(3)
);
InverterGenerated_4 : Inverter
port map (
I1 => output3,
clock => clock, O1 => Outputs(4)
);
InverterGenerated_5 : Inverter
port map (
I1 => output4,
clock => clock, O1 => Outputs(5)
);
InverterGenerated_6 : Inverter
port map (
I1 => output5,
clock => clock, O1 => Outputs(6)
);
InverterGenerated_7 : Inverter
port map (
I1 => output6,
clock => clock, O1 => Outputs(7)
);
InverterGenerated_8 : Inverter
port map (
I1 => output7,
clock => clock, O1 => Outputs(8)
);
end Behaviour;
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity Inverter is
port ( I1 : std_logic ;
clock : in std_logic;
O1 : out std_logic );
end Inverter;
Architecture Behav of Inverter is

begin
process (I1,clock)
begin
if (clock'EVENT and clock='1') then
O1 <= not (I1);
end if;
end process ;
end Behav;
Click to expand...
 
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