Error:Case expression must be of a locally static subtype.

[Mohammed A khader]

Hi All,

When simulating the following piece of code I came across this
Error: COMP96_0316: Sincos_Rom.vhd : (37, 22): Case expression must be
of a locally static subtype.

In case statement I am concatenating 3 std_logic types to a vector of
signed type of length 3.It is clear from the defination that vector is
static (that is vector length is locally fixed as 3 ).
In order to force the singed vector to 3 I changed it to follwoing
expression
case signed(2 downto 0)'( Sincos_Sel & negate & image) is ...

but still some other syntax error was displayed.
Error: COMP96_0015: Sincos_Rom.vhd : (37, 31): ')' expected.

Please help me in understanding it...

Code is here ......


Operation_Sel:case signed'( Sincos_Sel & negate & image) is

when "000" =>
shift := '0';
complement := '0';

when "001" =>
shift := '1';
complement := '0';

when "010" =>
shift := '0';
complement := '1';

when "011" =>
shift := '1';
complement := '1';

when "100" =>
shift := '1';
complement := '0';

when others =>
shift := 'X';
complement := 'X';
end case Operation_Sel;

Thanks,

Mohammed Khader.

 

[Jonathan Bromley]

On 28 Jan 2005 02:46:44 -0800, "Mohammed A khader"
<am.imak@gmail.com> wrote:

Hi All,

When simulating the following piece of code I came across this
Error: COMP96_0316: Sincos_Rom.vhd : (37, 22): Case expression must be
of a locally static subtype.

In case statement I am concatenating 3 std_logic types to a vector of
signed type of length 3.It is clear from the defination that vector is
static (that is vector length is locally fixed as 3 ).

Yes, but its subtype is not static. Irritating but true.
Some simulators have a compiler switch that allows this
illegal VHDL to be tolerated, and I think the VHDL-200x "fast track"
working group has proposed it as a future relaxation of the rules.
But for the time being you need to fix it yourself.

In order to force the singed vector to 3 I changed it to follwoing
expression
case signed(2 downto 0)'( Sincos_Sel & negate & image) is ...

but still some other syntax error was displayed.

You're on the right track, but the type-qualification
syntax T'(expr) requires a subtype name. So you need
to do something like....

process (....)
subtype SGN3 is signed(2 downto 0);
begin
...
case SGN3'(Sincos_Sel & negate & image) is ...

Even better, choose a nice meaningful name for your subtype!
--
Jonathan Bromley, Consultant

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