Error 10170 syntax error during compilation

[Jughead]

I am new to verilog. It gives a compilation error for the if statement.
Could someone help me out by pointing out my mistake?.

reg [2:0] next_state, current_state;
parameter reset_state = 3'b000;

always @(posedge clock)
case (datain)
0:
{
if (current_state == reset_state)
begin
{
next_state = reset_state;
}
end

This is a part of code that I have written. It gives the following
error

Error (10170): Verilog HDL syntax error at seqdet.v(24) near text "if";
expecting an identifier ("if" is a reserved keyword ), or a number, or
a system task, or "(", or "{", or unary operator,

current_state is of register type and reset_state has been intialized
to 3'b000 using parameter statement.

Thanks,
Aravind

 

[Jughead]

Jughead wrote:

I am new to verilog. It gives a compilation error for the if statement.
Could someone help me out by pointing out my mistake?.

reg [2:0] next_state, current_state;
parameter reset_state = 3'b000;

always @(posedge clock)
case (datain)
0:
{
if (current_state == reset_state)
begin
{
next_state = reset_state;
}
end

This is a part of code that I have written. It gives the following
error

Error (10170): Verilog HDL syntax error at seqdet.v(24) near text "if";
expecting an identifier ("if" is a reserved keyword ), or a number, or
a system task, or "(", or "{", or unary operator,

current_state is of register type and reset_state has been intialized
to 3'b000 using parameter statement.

Thanks,
Aravind

Found out that case statement didn't have a begin and end statements
and they had braces which I don't think were required. Not sure if I am
right. But I am not getting the error now.

-Aravind

 

[Michael]

{} are used for bit concatenation. Use "begin end" instead.
Don't forget "endcase" as well.

 

[Michael]

{} are used for bit concatenation. Use "begin end" instead.
Don't forget "endcase" as well.