X
Xiaofeng Wang
Guest
Hi, all:
I have a question on the effective width of a transistor layout.
the layout is at http://wangxf.nease.net/temp/transistor.bmp
(The drawing is not to scale, the shape is actually a square.)
I drawed the layout in cadence and did the extraction. Cadence gave an
effective transistor. The effective width is around 47um, while the effective
length is around 0.5um.
I know the effective width is due to the corner effect.
But I have some confusion about the effective length. Why it is half of the
physical length. I tried different length, and it seemed the effective length
is always half of the physical length. Can anyone tell me why? Is Cadence
extraction accurate?
Thanks.
Best Regards,
Xiaofeng
I have a question on the effective width of a transistor layout.
the layout is at http://wangxf.nease.net/temp/transistor.bmp
(The drawing is not to scale, the shape is actually a square.)
I drawed the layout in cadence and did the extraction. Cadence gave an
effective transistor. The effective width is around 47um, while the effective
length is around 0.5um.
I know the effective width is due to the corner effect.
But I have some confusion about the effective length. Why it is half of the
physical length. I tried different length, and it seemed the effective length
is always half of the physical length. Can anyone tell me why? Is Cadence
extraction accurate?
Thanks.
Best Regards,
Xiaofeng