equivalent of defparam in vhdl.

[kk]

For one of my program, i use defparam in verilog to set a parameter
which is one level below the hierarchy. I've three modules A, B, C. The
C is instantiated in B, B in A. There is a parameter in C which is not
brought out to B. I dont have the permission to modify B and C by any
chance. In verilog i can set the parameter by using a defparam
statement in A.
Is there way i could do this in VHDL, if all the three are in VHDL.

thanks in adv.

 

[Ajeetha]

Hi KK,
If this is for Synthesis, it is a bad style - usually defparam is
unsupported in synth tools. If it is for pure simulation alone,
simulators provide a way to override generics from command line.
Typically the option is "-g".

Read your tool's doc for more.

HTH
Ajeetha, CVC
www.noveldv.com
www.systemverilog.us

kk wrote:

For one of my program, i use defparam in verilog to set a parameter
which is one level below the hierarchy. I've three modules A, B, C. The
C is instantiated in B, B in A. There is a parameter in C which is not
brought out to B. I dont have the permission to modify B and C by any
chance. In verilog i can set the parameter by using a defparam
statement in A.
Is there way i could do this in VHDL, if all the three are in VHDL.

thanks in adv.

 

[kk]

Hi,

First of this is only for simulation and not for synthesis.
Secondly, i dont think i can use the -g option, as the problem is with
wrapper + smart models rather than actual vhdl files.

thanks....

Ajeetha wrote:

Hi KK,
If this is for Synthesis, it is a bad style - usually defparam is
unsupported in synth tools. If it is for pure simulation alone,
simulators provide a way to override generics from command line.
Typically the option is "-g".

Read your tool's doc for more.

HTH
Ajeetha, CVC
www.noveldv.com
www.systemverilog.us

kk wrote:
For one of my program, i use defparam in verilog to set a parameter
which is one level below the hierarchy. I've three modules A, B, C. The
C is instantiated in B, B in A. There is a parameter in C which is not
brought out to B. I dont have the permission to modify B and C by any
chance. In verilog i can set the parameter by using a defparam
statement in A.
Is there way i could do this in VHDL, if all the three are in VHDL.

thanks in adv.

 

[Rob Dekker]

"Ajeetha" <ajeetha@gmail.com> wrote in message news:1154434151.861850.278520@s13g2000cwa.googlegroups.com...

Hi KK,
If this is for Synthesis, it is a bad style - usually defparam is
unsupported in synth tools.

Actually defparam is supported for most synthesis tools that I know of.
Although not without pain and suffering for the synthesis compiler implementers (

Note that defparam is scheduled to be removed from the Verilog language..
Not that that has much effect : it is used in almost all Verilog designs, due
to the primitive start of Verilog.

Rob

 

[Rob Dekker]

"kk" <bkkishore@gmail.com> wrote in message news:1154409066.031929.32490@75g2000cwc.googlegroups.com...

For one of my program, i use defparam in verilog to set a parameter
which is one level below the hierarchy. I've three modules A, B, C. The
C is instantiated in B, B in A. There is a parameter in C which is not
brought out to B. I dont have the permission to modify B and C by any
chance. In verilog i can set the parameter by using a defparam
statement in A.
Is there way i could do this in VHDL, if all the three are in VHDL.

thanks in adv.

From A you want to control a parameter in C, so that is TWO levels deep into the hierarchy.

I believe that you can do this nicely with a configuration of A, although I have not tried it out :
Here are the crucial parts of the configuration :

configuration foo of A is
...
for instance_name_of_B_in_A
..
for instance_name_of_C_in_B
use work.C generic map (Cs_parameter => As_param_value) ..
end configuration ;

I think As_param_value can even be an expression in terms of generics in either A or even B
which are up in the hierarchy path when this configuration hits.
That is because both B's and A's scope (name space) are made visible in the component configuration.

This means that you can actually do more than the Verilog defparam.

Rob