Enum type as array range

[rickman]

Maybe I am being a little dense, but I can't find anything on this in my
VHDL books and the LRM is pretty esoteric in this section.

I am writing some code to help me simplify simulation data display and I
want to have some SLV constants in an array. These constants relate to
defined states of a combination of signals and have names associated
with them. To get the names to show up in the simulation, I want to use
an enumerated type which then corresponds to the index of the constant
array.

Can I directly use this enumerated type as the index? I am still a day
or so from having some code to try. Am I barking up the wrong tree with
this? Should I convert my enum variable to an int and use that as the
array index?


subtype ALUSLV is SLV07;
subtype ALUTyp is (AD, ADC, SU, SUC, CM, CMC, AN, LOR, LXR, SR, SC,
AER);

type ALUstyles is array (ALUTyp) of ALUSLV := (
"00100XX", ...


--

Rick "rickman" Collins

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[Mike Treseler]

rickman wrote:

I am writing some code to help me simplify simulation data display and I
want to have some SLV constants in an array. These constants relate to
defined states of a combination of signals and have names associated
with them. To get the names to show up in the simulation, I want to use
an enumerated type which then corresponds to the index of the constant
array.
Can I directly use this enumerated type as the index?

yes

I am still a day
or so from having some code to try. Am I barking up the wrong tree with
this?

No, it's a good idea.

Should I convert my enum variable to an int and use that as the
array index?
subtype ALUSLV is SLV07;
subtype ALUTyp is (AD, ADC, SU, SUC, CM, CMC, AN, LOR, LXR, SR, SC,AER);

type ALUstyles is array (ALUTyp) of ALUSLV := (
"00100XX", ...

I see. Maybe like this:
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity alu_test is
end alu_test;
-------------------------------------------------------------------------------
architecture sim of alu_test is
subtype ALUSLV is std_logic_vector(7 downto 0);
type ALUTyp is (AD, ADC, SU, SUC, CM, CMC, AN, LOR, LXR, SR, SC, AER);
type ALUstyles is array (ALUTyp'left to ALUTyp'right) of ALUSLV;
constant init : ALUstyles := (AD => x"42", ADC => x"ff", others => x"00");
begin
-- sim processes
end architecture sim;

-- Mike Treseler