ENUM IN INTERFACE (SYS VLOG)

[terabits]

Hi

This is about usage of enum in interface..im seeing strange
errors !!!
pls see the following code

interface xclr;
typedef enum {red,blue,green} color;
color type1,type2;
modports tr1 (input type1,output type2....)
.....
endinterface

module tr1_type (xclr x,...);
typedef x.color clr; // here i am seeing an error saying x.color is
not visible
clr c1,c2,c3...;
//usage
assgin xyz = c1.blue ; // can i do this ?? (i want to assign ethe
value to some internal code)
assign x.type2 = 2; // output assignement (assign the output in the
interface with some value)
endmodule

test....
....xclr x1;
tr1_type tr (x1,...)
endmodule

rgds

 

terabits wrote:

typedef x.color clr; // here i am seeing an error saying x.color is
not visible

I don't believe you can make a hierarchical reference to a type,
though perhaps there is an exception for interfaces. I would
suggest you put the type into a package, and import it into the
interface and the module.

assgin xyz = c1.blue ; // can i do this ?? (i want to assign ethe
value to some internal code)

Should be legal. If xyz is not an enum, you should
get the numeric value for blue.

assign x.type2 = 2; // output assignement (assign the output in the
interface with some value)

Technically illegal, since x.type2 is of an enum type, so
you cannot assign anything to it that is not of that type.

 

[terabits]

Accellera Extensions to Verilog-2001 SystemVerilog 3.1a
interface intf_i;
typedef int data_t;
endinterface
module sub(intf_i p)
typedef p.data_t my_data_t;
my_data_t data; //
type of data will be int when connected to interface above
endmodule

I don't believe you can make a hierarchical reference to a type,
though perhaps there is an exception for interfaces. I would
suggest you put the type into a package, and import it into the
interface and the module.

the above example is direclty from the lrm 3rd chapter..i kinda
followed it.

assgin xyz = c1.blue ; // can i do this ?? (i want to assign ethe
value to some internal code)

Should be legal. If xyz is not an enum, you should
get the numeric value for blue.

assign x.type2 = 2; // output assignement (assign the output in the
interface with some value)

yeah i cannot assign this...

x.type2 = c2.blue would be fine right ?

shall check the package for this..thnq...

rgds

 

[Jonathan Bromley]

On 16 Feb 2007 13:12:04 -0800, "terabits"
<tera.bits@gmail.com> wrote:

There were some ambiguities and typos in your example
so I rewrote and simplified it:

interface xclr;
typedef enum {red,blue,green} color;
color type1,type2;
endinterface

module tr1_type (xclr x);
typedef x.color clr;
clr c1;
initial begin
c1 = x.red;
$display(c1.name);
end
endmodule

module test;
xclr x1();
tr1_type tr (x1);
endmodule

This compiled and ran OK in one simulator I tried.
A second simulator processed the hierarchical typedef
correctly, but doesn't yet support hierarchical reference
to enum literals in an interface, so I hacked the first line
of the initial block...
c1 = clr'(0);
and then it worked OK.

As far as I know, you can't (at present) see type and enum
names through a modport. There's been some discussion of
this on the SysVerilog standards committees but I haven't
tracked it down; I'll take another look over the weekend.

Wouldn't it be better to define the enum in a package?
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[terabits]

this also didn't work with my simulator.....
yeah i proceeded with package and it is working fine now...
i wanted to make my code look fancy with enum modports in interface so
initially tried 'em

thnks anyways..have a great weekend

rgds

There were some ambiguities and typos in your example
so I rewrote and simplified it:

interface xclr;
typedef enum {red,blue,green} color;
color type1,type2;
endinterface

module tr1_type (xclr x);
typedef x.color clr;
clr c1;
initial begin
c1 = x.red;
$display(c1.name);
end
endmodule

module test;
xclr x1();
tr1_type tr (x1);
endmodule

This compiled and ran OK in one simulator I tried.
A second simulator processed the hierarchical typedef
correctly, but doesn't yet support hierarchical reference
to enum literals in an interface, so I hacked the first line
of the initial block...
c1 = clr'(0);
and then it worked OK.

As far as I know, you can't (at present) see type and enum
names through a modport. There's been some discussion of
this on the SysVerilog standards committees but I haven't
tracked it down; I'll take another look over the weekend.

Wouldn't it be better to define the enum in a package?
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.