entity component binding issue with configurations

[Marvin L]

I have binding warnings http://paste2.org/La9jIxbF with http://paste2.org/wnHDY0g3 How do I solve them ? even I modify the configuration as in http://paste2.org/bJZJPdWt , I have this error http://paste2.org/BLW1yg32

 

[Allan Herriman]

On Sun, 23 Oct 2016 00:15:03 -0700, Marvin L wrote:

I have binding warnings http://paste2.org/La9jIxbF with
http://paste2.org/wnHDY0g3 How do I solve them ? even I modify the
configuration as in http://paste2.org/bJZJPdWt , I have this error
http://paste2.org/BLW1yg32

The first error message:
key_expansion.vhd:46:1:warning: 's0' is not bound

Line 46 looks like this:
s0: subbytes port map ( sbox_in => tmp_w(23 downto 16) , sbox_out =>
subword(31 downto 24) );

Your component declaration looks ok (based on what I would expect subbytes
to look like).

Did you remember to compile subbytes.vhd?


BTW, you can download free versions of AES crypto engine VHDL source in
all shapes an sizes. Many of them will even work correctly.

Regards,
Allan

 

[Marvin L]

On Sunday, October 23, 2016 at 5:17:57 PM UTC+8, Allan Herriman wrote:

On Sun, 23 Oct 2016 00:15:03 -0700, Marvin L wrote:

I have binding warnings http://paste2.org/La9jIxbF with
http://paste2.org/wnHDY0g3 How do I solve them ? even I modify the
configuration as in http://paste2.org/bJZJPdWt , I have this error
http://paste2.org/BLW1yg32


The first error message:
key_expansion.vhd:46:1:warning: 's0' is not bound

Line 46 looks like this:
s0: subbytes port map ( sbox_in => tmp_w(23 downto 16) , sbox_out =
subword(31 downto 24) );

Your component declaration looks ok (based on what I would expect subbytes
to look like).

Did you remember to compile subbytes.vhd?


BTW, you can download free versions of AES crypto engine VHDL source in
all shapes an sizes. Many of them will even work correctly.

Regards,
Allan

I have solved the problem. I forgot to compile subbytes.vhd and round_constant.vhd together with key_expansion.vhd but in gHDL, I open in .ghw format but I still could not view internal signals such as w0, w1, w2, w3, temp_w WHY ?

 

[Marvin L]

On Sunday, October 23, 2016 at 11:49:37 PM UTC+8, Marvin L wrote:

On Sunday, October 23, 2016 at 5:17:57 PM UTC+8, Allan Herriman wrote:
On Sun, 23 Oct 2016 00:15:03 -0700, Marvin L wrote:

I have binding warnings http://paste2.org/La9jIxbF with
http://paste2.org/wnHDY0g3 How do I solve them ? even I modify the
configuration as in http://paste2.org/bJZJPdWt , I have this error
http://paste2.org/BLW1yg32


The first error message:
key_expansion.vhd:46:1:warning: 's0' is not bound

Line 46 looks like this:
s0: subbytes port map ( sbox_in => tmp_w(23 downto 16) , sbox_out =
subword(31 downto 24) );

Your component declaration looks ok (based on what I would expect subbytes
to look like).

Did you remember to compile subbytes.vhd?


BTW, you can download free versions of AES crypto engine VHDL source in
all shapes an sizes. Many of them will even work correctly.

Regards,
Allan

I have solved the problem. I forgot to compile subbytes.vhd and round_constant.vhd together with key_expansion.vhd but in gHDL, I open in .ghw format but I still could not view internal signals such as w0, w1, w2, w3, temp_w WHY ?

I could not view the internal signal http://i.imgur.com/w4jwnN1.png even though I am using the formal format *ghw with http://paste2.org/mVMOJZYA , http://paste2.org/vpbvXcID , http://paste2.org/1pAZac73 , http://paste2.org/FDh4c6Av and http://paste2.org/UwgnBnds