`endif question....

[johnp]

I looking at some Verilog code that I believe is legal but one of my
tools complains about. The code used `ifdef...`endif constructs to
select signals to pass to a module for different configurations.

The problem pops up at the very end of a module instantiation:

// instantiate the module
my_mod u_my_mod (
`ifdef foo
.p1 (param1a),
.p2 (param2a),
.p3 (param3a)
`else
.p1 (param1b),
.p2 (param2b),
.p3 (param3b)
`endif );

Note the ");" immediately after the `endif. A gross coding style, but
I
believe this is legal.

Any opinions on if this style is OK?

Thanks!

John Providenza

 

[Jonathan Bromley]

On Mon, 11 Feb 2008 10:53:21 -0800 (PST), johnp
<johnp3+nospam@probo.com> wrote:

Note the ");" immediately after the `endif. A gross coding style, but
I believe this is legal.

I don't know, but my first resort would be to put the
`endif on a line of its own - there is surely no reason
why the `endif and closing paren need to be on the same
physical line?
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[johnp]

On Feb 11, 11:34 am, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
wrote:

On Mon, 11 Feb 2008 10:53:21 -0800 (PST), johnp

johnp3+nos...@probo.com> wrote:
Note the ");" immediately after the `endif. A gross coding style, but
I believe this is legal.

I don't know, but my first resort would be to put the
`endif on a line of its own - there is surely no reason
why the `endif and closing paren need to be on the same
physical line?
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

Jonathan -

That's what I did to solve the problem, I'm just curious about if
it is legal or not.

It's certainly ugly.

John P

 

[Mark McDougall]

johnp wrote:

// instantiate the module
my_mod u_my_mod (
`ifdef foo
.p1 (param1a),
.p2 (param2a),
.p3 (param3a)
`else
.p1 (param1b),
.p2 (param2b),
.p3 (param3b)
`endif );

Yuck! Yuck! Yuck!

'ifdef foo
param1 = param1a;
param2 = param2a;
param3 = param3a;
'else
param1 = param1b;
param2 = param2b;
param3 = param3b;
'endif

my_mod u_my_mod
(
.p1 (param1),
.p2 (param2),
.p3 (param3)
);

Regards,

--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266

 

[johnp]

On Feb 11, 3:41 pm, Mark McDougall <ma...@vl.com.au> wrote:

johnp wrote:
// instantiate the module
my_mod u_my_mod (
`ifdef foo
.p1 (param1a),
.p2 (param2a),
.p3 (param3a)
`else
.p1 (param1b),
.p2 (param2b),
.p3 (param3b)
`endif );

Yuck! Yuck! Yuck!

'ifdef foo
param1 = param1a;
param2 = param2a;
param3 = param3a;
'else
param1 = param1b;
param2 = param2b;
param3 = param3b;
'endif

my_mod u_my_mod
(
.p1 (param1),
.p2 (param2),
.p3 (param3)
);

Regards,

--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266

Yes, I KNOW the original code is awful! It's in an IP block I
need to use.

My question is, is having the `endif); LEGAL? I know it's gross, but
is it legal?

John P

 

On Feb 11, 9:26 pm, johnp <johnp3+nos...@probo.com> wrote:

My question is, is having the `endif); LEGAL?  I know it's gross, but
is it legal?

The LRM does not address this, so it is unclear.

A lot of the descriptions of compiler directives seem to assume that
they will appear on lines by themselves. For example, the description
of `ifdef talks about including or not including source lines, not
source text. This suggests that source text on the `ifdef line after
the macro name would not be included, or would be illegal. This
further suggests that any text on the same line as these directives
would be discarded or illegal.

There is a statement that these directives are allowed anywhere in the
source, but that was probably intended to mean that they were not
restricted to inside modules or outside modules, as some other
directives are.

A test of the original de facto standard, Verilog-XL, indicates that
it will allow the text after the `endif, and include it in the
design. However, there are other cases where XL allows things that
the LRM clearly does not.

Sorry I can't give you a more precise answer, but the Verilog LRM is
imprecise in many areas.