encryption algorithms

[abhinav]

hi there
i was just hoping to implement a encryption algorithm in VHDL. But i
can't understand how to analyze the performance of the algorithm from
the timing digs generated. That wud just give me the latency time,
right?
Also i'm not really sure about the software to use, Any suggestions?
Any help would b gratefully accepted. thanx

 

Timing diagrams not only tell you about latency but also how the design
is implemented as far as inputs and processing are concerned.

-Neo

 

[Mike Treseler]

abhinav wrote:

i was just hoping to implement a encryption algorithm in VHDL. But i
can't understand how to analyze the performance of the algorithm from
the timing digs generated.

throughput: bits per second in and out
latency: time it takes some set of bits to pass through.

The best performance possible is encryption
of the entire message in one clock tick.
However it is unlikely that you have enough
device pins or logic cells to handle that.

So you make some engineering choices.
Input and output width.
Number of pipeline stages etc.
Read up on parallel CRC generation
as this has the same design issues.

Also i'm not really sure about the software to use, Any suggestions?

Consider modelsim or sonata for functional sim.
Check static timing using your FPGA place and route.

-- Mike Treseler