Guest
I have a old verilog-style testbench (as modules), for a "core".
I want to "encapsulate" this in a class in some way.
There are tasks in the old testbench i want to "virtualize", so they
can be overridden by inheriting classes.
These virtualized "base" functions should communicate with the "core",
what was done by the old verilog-style testbench directly. But the
"core" is now deeper hidden in hierarchy behind extra modules and
possibly instantiated multiple times.
But unfortunately i can't simply "encapsulate" the old testbench in a
class to do what i described.
Am i thinking in the wrong direction?
What could be a way to achieve my goal?
My experience with SV seems too limited.
Raymund Hofmann
I want to "encapsulate" this in a class in some way.
There are tasks in the old testbench i want to "virtualize", so they
can be overridden by inheriting classes.
These virtualized "base" functions should communicate with the "core",
what was done by the old verilog-style testbench directly. But the
"core" is now deeper hidden in hierarchy behind extra modules and
possibly instantiated multiple times.
But unfortunately i can't simply "encapsulate" the old testbench in a
class to do what i described.
Am i thinking in the wrong direction?
What could be a way to achieve my goal?
My experience with SV seems too limited.
Raymund Hofmann