eliminating a DDS

[John Larkin]

I have a design that will use a DDS synthesizer to generate an
internal trigger rate for a pulse generator. The chip will be a ZYNQ
7020. The required upper frequency limit is maybe 20 MHz. The FPGA
will have the usual, 48 bit or so, phase accumulator and sine lookup
stuff clocked at maybe 100 MHz. The FPGA drives a fast DAC which in
turn drives an LC lowpass filter and a comparator. Standard stuff.

But could such a clock be generated entirely inside the FPGA?

Just using the MSB of the DDS phase accumulator works, but it will
have one full clock, 10 ns p-p, of jitter. That will be ugly at 20
MHz. I've got to look into some sort of outboard analog filtering to
clean up that single-bit clock, but I'm not optimistic. DDS is just
too weird.

Do you suppose that one of the FPGA PLLs be used to clean up the DDS
clock, scrub the jitter somehow? That could maybe be used over a
modest range, octave maybe, followed by some dividers.

Any other ideas for making a programmable-frequency clock with DDS
sort of resolution, but without all that outboard analog stuff?

I've been playing with sorta DDS in LT Spice, using a quantizer to
approximate the DDS accumulator and DAC, but that's obviously not the
best tool for this.



--

John Larkin Highland Technology, Inc

lunatic fringe electronics

 

Den søndag den 4. september 2016 kl. 20.11.40 UTC+2 skrev John Larkin:

I have a design that will use a DDS synthesizer to generate an
internal trigger rate for a pulse generator. The chip will be a ZYNQ
7020. The required upper frequency limit is maybe 20 MHz. The FPGA
will have the usual, 48 bit or so, phase accumulator and sine lookup
stuff clocked at maybe 100 MHz. The FPGA drives a fast DAC which in
turn drives an LC lowpass filter and a comparator. Standard stuff.

But could such a clock be generated entirely inside the FPGA?

Just using the MSB of the DDS phase accumulator works, but it will
have one full clock, 10 ns p-p, of jitter. That will be ugly at 20
MHz. I've got to look into some sort of outboard analog filtering to
clean up that single-bit clock, but I'm not optimistic. DDS is just
too weird.

Do you suppose that one of the FPGA PLLs be used to clean up the DDS
clock, scrub the jitter somehow? That could maybe be used over a
modest range, octave maybe, followed by some dividers.

Any other ideas for making a programmable-frequency clock with DDS
sort of resolution, but without all that outboard analog stuff?

I've been playing with sorta DDS in LT Spice, using a quantizer to
approximate the DDS accumulator and DAC, but that's obviously not the
best tool for this.

you might be able to do something with the clock manager PLL, it does have
a jitter filter mode but I haven't had any reason to look at how it works

other trickery you could do is

use an DDR output flop to get double resolution or more with a faster clock
use some trickery with pll and serdes output

-Lasse

 

[Mike Perkins]

On 04/09/2016 19:11, John Larkin wrote:

I have a design that will use a DDS synthesizer to generate an
internal trigger rate for a pulse generator. The chip will be a ZYNQ
7020. The required upper frequency limit is maybe 20 MHz. The FPGA
will have the usual, 48 bit or so, phase accumulator and sine lookup
stuff clocked at maybe 100 MHz. The FPGA drives a fast DAC which in
turn drives an LC lowpass filter and a comparator. Standard stuff.

But could such a clock be generated entirely inside the FPGA?

Just using the MSB of the DDS phase accumulator works, but it will
have one full clock, 10 ns p-p, of jitter. That will be ugly at 20
MHz. I've got to look into some sort of outboard analog filtering to
clean up that single-bit clock, but I'm not optimistic. DDS is just
too weird.

Do you suppose that one of the FPGA PLLs be used to clean up the DDS
clock, scrub the jitter somehow? That could maybe be used over a
modest range, octave maybe, followed by some dividers.

That isn't how FPGA PLLs work. They add jitter rather than removing it!

Any other ideas for making a programmable-frequency clock with DDS
sort of resolution, but without all that outboard analog stuff?

I've been playing with sorta DDS in LT Spice, using a quantizer to
approximate the DDS accumulator and DAC, but that's obviously not the
best tool for this.

The jitter of a clock derived from within a FPGA would simply be related
to the clock frequency used.

If you use a 250MHz clock, as per the max frequency of many cheap FPGAs,
then jitter will be 4ns (+ a small bit).

What jitter spec are you looking for? What is the range of frequencies
you require?

Would a VCO / PLL be a better bet to filter the digital jitter, using
the MSB of your phase accumulator as the reference?

--
Mike Perkins
Video Solutions Ltd
www.videosolutions.ltd.uk

 

[John Larkin]

On Sun, 4 Sep 2016 20:13:04 +0100, Mike Perkins <spam@spam.com> wrote:

On 04/09/2016 19:11, John Larkin wrote:


I have a design that will use a DDS synthesizer to generate an
internal trigger rate for a pulse generator. The chip will be a ZYNQ
7020. The required upper frequency limit is maybe 20 MHz. The FPGA
will have the usual, 48 bit or so, phase accumulator and sine lookup
stuff clocked at maybe 100 MHz. The FPGA drives a fast DAC which in
turn drives an LC lowpass filter and a comparator. Standard stuff.

But could such a clock be generated entirely inside the FPGA?

Just using the MSB of the DDS phase accumulator works, but it will
have one full clock, 10 ns p-p, of jitter. That will be ugly at 20
MHz. I've got to look into some sort of outboard analog filtering to
clean up that single-bit clock, but I'm not optimistic. DDS is just
too weird.

Do you suppose that one of the FPGA PLLs be used to clean up the DDS
clock, scrub the jitter somehow? That could maybe be used over a
modest range, octave maybe, followed by some dividers.

That isn't how FPGA PLLs work. They add jitter rather than removing it!

We did one clock X2 multiply with a Xilinx DLL, 40 ==> 80 MHz, and the
resulting clock period was bimodal, about 80 ps or so. Ugly. The
actual jitter, ignoring the bimode, wasn't bad.

Any other ideas for making a programmable-frequency clock with DDS
sort of resolution, but without all that outboard analog stuff?

I've been playing with sorta DDS in LT Spice, using a quantizer to
approximate the DDS accumulator and DAC, but that's obviously not the
best tool for this.

The jitter of a clock derived from within a FPGA would simply be related
to the clock frequency used.

If you use a 250MHz clock, as per the max frequency of many cheap FPGAs,
then jitter will be 4ns (+ a small bit).

What jitter spec are you looking for? What is the range of frequencies
you require?

Picoseconds of period jitter would be nice!

Would a VCO / PLL be a better bet to filter the digital jitter, using
the MSB of your phase accumulator as the reference?

Or maybe a filter and comparator? Instinct suggests that would be
mediocre. The real advantage of outboard DDS-MSB clock cleanup is all
those DAC pins saved; probably no cost advantage.

This was a longshot question, just to see if there was some clever
trick lurking somewhere.



--

John Larkin Highland Technology, Inc

lunatic fringe electronics

 

[Tom Gardner]

On 04/09/16 19:11, John Larkin wrote:

Do you suppose that one of the FPGA PLLs be used to clean up the DDS
clock, scrub the jitter somehow? That could maybe be used over a
modest range, octave maybe, followed by some dividers.

*IIRC* you have to use the Xilinx clocking wizard (part
of ISE or Vivado), and the SERDES blocks' multipliers have
a jitter of 150-200ps.

 

[Tim Wescott]

On Sun, 04 Sep 2016 11:11:32 -0700, John Larkin wrote:

I have a design that will use a DDS synthesizer to generate an internal
trigger rate for a pulse generator. The chip will be a ZYNQ 7020. The
required upper frequency limit is maybe 20 MHz. The FPGA will have the
usual, 48 bit or so, phase accumulator and sine lookup stuff clocked at
maybe 100 MHz. The FPGA drives a fast DAC which in turn drives an LC
lowpass filter and a comparator. Standard stuff.

But could such a clock be generated entirely inside the FPGA?

Just using the MSB of the DDS phase accumulator works, but it will have
one full clock, 10 ns p-p, of jitter. That will be ugly at 20 MHz. I've
got to look into some sort of outboard analog filtering to clean up that
single-bit clock, but I'm not optimistic. DDS is just too weird.

Do you suppose that one of the FPGA PLLs be used to clean up the DDS
clock, scrub the jitter somehow? That could maybe be used over a modest
range, octave maybe, followed by some dividers.

Any other ideas for making a programmable-frequency clock with DDS sort
of resolution, but without all that outboard analog stuff?

I've been playing with sorta DDS in LT Spice, using a quantizer to
approximate the DDS accumulator and DAC, but that's obviously not the
best tool for this.

I sat in on a seminar on using FPGAs in comms circuits once, a long time
ago. I made some comment that essentially boiled down to "trust the FPGA
clock to not jitter", and was hooted down by the entire audience.

I haven't forgotten...

--
Tim Wescott
Control systems, embedded software and circuit design
I'm looking for work! See my website if you're interested
http://www.wescottdesign.com

 

Maybe you get a better jitter than the MSB by using an iodelay oscillator. Never done this, but xapp872 describes it.

 

[rickman]

On 9/4/2016 3:13 PM, Mike Perkins wrote:

On 04/09/2016 19:11, John Larkin wrote:


I have a design that will use a DDS synthesizer to generate an
internal trigger rate for a pulse generator. The chip will be a ZYNQ
7020. The required upper frequency limit is maybe 20 MHz. The FPGA
will have the usual, 48 bit or so, phase accumulator and sine lookup
stuff clocked at maybe 100 MHz. The FPGA drives a fast DAC which in
turn drives an LC lowpass filter and a comparator. Standard stuff.

But could such a clock be generated entirely inside the FPGA?

Just using the MSB of the DDS phase accumulator works, but it will
have one full clock, 10 ns p-p, of jitter. That will be ugly at 20
MHz. I've got to look into some sort of outboard analog filtering to
clean up that single-bit clock, but I'm not optimistic. DDS is just
too weird.

Do you suppose that one of the FPGA PLLs be used to clean up the DDS
clock, scrub the jitter somehow? That could maybe be used over a
modest range, octave maybe, followed by some dividers.

That isn't how FPGA PLLs work. They add jitter rather than removing it!

Aren't you thinking of a digital PLL? The PLL in FPGAs is typically a
standard analog PLL and so *would* remove jitter.

Any other ideas for making a programmable-frequency clock with DDS
sort of resolution, but without all that outboard analog stuff?

I've been playing with sorta DDS in LT Spice, using a quantizer to
approximate the DDS accumulator and DAC, but that's obviously not the
best tool for this.

The jitter of a clock derived from within a FPGA would simply be related
to the clock frequency used.

If you use a 250MHz clock, as per the max frequency of many cheap FPGAs,
then jitter will be 4ns (+ a small bit).

Yes, you are clearly thinking of a digital PLL based on the digital
fabric of the FPGA. I assume John was talking about the dedicated PLLs
found in most FPGAS.

What jitter spec are you looking for? What is the range of frequencies
you require?

Would a VCO / PLL be a better bet to filter the digital jitter, using
the MSB of your phase accumulator as the reference?

--

Rick C

 

[Mike Perkins]

On 05/09/2016 11:57, rickman wrote:

On 9/4/2016 3:13 PM, Mike Perkins wrote:
On 04/09/2016 19:11, John Larkin wrote:


I have a design that will use a DDS synthesizer to generate an
internal trigger rate for a pulse generator. The chip will be a ZYNQ
7020. The required upper frequency limit is maybe 20 MHz. The FPGA
will have the usual, 48 bit or so, phase accumulator and sine lookup
stuff clocked at maybe 100 MHz. The FPGA drives a fast DAC which in
turn drives an LC lowpass filter and a comparator. Standard stuff.

But could such a clock be generated entirely inside the FPGA?

Just using the MSB of the DDS phase accumulator works, but it will
have one full clock, 10 ns p-p, of jitter. That will be ugly at 20
MHz. I've got to look into some sort of outboard analog filtering to
clean up that single-bit clock, but I'm not optimistic. DDS is just
too weird.

Do you suppose that one of the FPGA PLLs be used to clean up the DDS
clock, scrub the jitter somehow? That could maybe be used over a
modest range, octave maybe, followed by some dividers.

That isn't how FPGA PLLs work. They add jitter rather than removing it!

Aren't you thinking of a digital PLL? The PLL in FPGAs is typically a
standard analog PLL and so *would* remove jitter.


Any other ideas for making a programmable-frequency clock with DDS
sort of resolution, but without all that outboard analog stuff?

I've been playing with sorta DDS in LT Spice, using a quantizer to
approximate the DDS accumulator and DAC, but that's obviously not the
best tool for this.

The jitter of a clock derived from within a FPGA would simply be related
to the clock frequency used.

If you use a 250MHz clock, as per the max frequency of many cheap FPGAs,
then jitter will be 4ns (+ a small bit).

Yes, you are clearly thinking of a digital PLL based on the digital
fabric of the FPGA. I assume John was talking about the dedicated PLLs
found in most FPGAS.

Most of my experience is with Xilinx who I don't believe use analogue PLLs.

Most FPGA PLLs are based on a variable length ring of gates which will
have jitter as gates are switched in and out of the loop.

Can you provide an example of a truly analogue PLL in a mainstream FPGA?

--
Mike Perkins
Video Solutions Ltd
www.videosolutions.ltd.uk

 

[Allan Herriman]

On Sun, 04 Sep 2016 11:11:32 -0700, John Larkin wrote:

I have a design that will use a DDS synthesizer to generate an
internal trigger rate for a pulse generator. The chip will be a ZYNQ
7020. The required upper frequency limit is maybe 20 MHz. The FPGA
will have the usual, 48 bit or so, phase accumulator and sine lookup
stuff clocked at maybe 100 MHz. The FPGA drives a fast DAC which in
turn drives an LC lowpass filter and a comparator. Standard stuff.

But could such a clock be generated entirely inside the FPGA?

Just using the MSB of the DDS phase accumulator works, but it will
have one full clock, 10 ns p-p, of jitter. That will be ugly at 20
MHz. I've got to look into some sort of outboard analog filtering to
clean up that single-bit clock, but I'm not optimistic. DDS is just
too weird.

Do you suppose that one of the FPGA PLLs be used to clean up the DDS
clock, scrub the jitter somehow? That could maybe be used over a
modest range, octave maybe, followed by some dividers.

Any other ideas for making a programmable-frequency clock with DDS
sort of resolution, but without all that outboard analog stuff?

I've been playing with sorta DDS in LT Spice, using a quantizer to
approximate the DDS accumulator and DAC, but that's obviously not the
best tool for this.

Changing from a Zynq 7020 to a '030 or '015 would give you transceivers
(GTX or GTP, respectively). This allows you to position the output
transitions with much more precision.
This would reduce your purely digital DDS jitter from 10ns p-p down to
less than 100ps p-p (for the '030 GTX in mid-speed grade) or 160ps p-p
(for the '015 GTP in the fastest speed grade or ~270ps in the slowest
speed grade).

IOW, the '015 gives you about a 40 times reduction in p-p jitter for
about the same cost as the '020.
Plus, the higher effective sampling rate changes the spectral
characteristics of the jitter and you will find it easier to locate a
clean band in which to position your output signal.

You might be tempted to use one of the onboard PLLs to clean this up, but
they generate about that amount of jitter all by themselves, so there's
probably not much net gain in doing that (along with some pitfalls).


The transceivers have another advantage - they have independent power
supplies and PLLs so you won't have activity in the FPGA fabric causing
output jitter as you do with normal logic outputs.


I'm sure you (or someone in your company) will know how to connect up a
DDS to a transceiver to do this. Ask if you need hints.

Regards,
Allan

 

Den mandag den 5. september 2016 kl. 17.19.49 UTC+2 skrev rickman:

On 9/5/2016 7:47 AM, Mike Perkins wrote:
On 05/09/2016 11:57, rickman wrote:
On 9/4/2016 3:13 PM, Mike Perkins wrote:
On 04/09/2016 19:11, John Larkin wrote:


I have a design that will use a DDS synthesizer to generate an
internal trigger rate for a pulse generator. The chip will be a ZYNQ
7020. The required upper frequency limit is maybe 20 MHz. The FPGA
will have the usual, 48 bit or so, phase accumulator and sine lookup
stuff clocked at maybe 100 MHz. The FPGA drives a fast DAC which in
turn drives an LC lowpass filter and a comparator. Standard stuff.

But could such a clock be generated entirely inside the FPGA?

Just using the MSB of the DDS phase accumulator works, but it will
have one full clock, 10 ns p-p, of jitter. That will be ugly at 20
MHz. I've got to look into some sort of outboard analog filtering to
clean up that single-bit clock, but I'm not optimistic. DDS is just
too weird.

Do you suppose that one of the FPGA PLLs be used to clean up the DDS
clock, scrub the jitter somehow? That could maybe be used over a
modest range, octave maybe, followed by some dividers.

That isn't how FPGA PLLs work. They add jitter rather than removing it!

Aren't you thinking of a digital PLL? The PLL in FPGAs is typically a
standard analog PLL and so *would* remove jitter.


Any other ideas for making a programmable-frequency clock with DDS
sort of resolution, but without all that outboard analog stuff?

I've been playing with sorta DDS in LT Spice, using a quantizer to
approximate the DDS accumulator and DAC, but that's obviously not the
best tool for this.

The jitter of a clock derived from within a FPGA would simply be related
to the clock frequency used.

If you use a 250MHz clock, as per the max frequency of many cheap FPGAs,
then jitter will be 4ns (+ a small bit).

Yes, you are clearly thinking of a digital PLL based on the digital
fabric of the FPGA. I assume John was talking about the dedicated PLLs
found in most FPGAS.

Most of my experience is with Xilinx who I don't believe use analogue PLLs.

Most FPGA PLLs are based on a variable length ring of gates which will
have jitter as gates are switched in and out of the loop.

Can you provide an example of a truly analogue PLL in a mainstream FPGA?

Xilinx uses a DLL, but I thought they also had a PLL capability.
Everyone else uses a PLL. Lattice data sheet for the XP2 says...

used to use a DLL, I am quite sure Zynq has a real pll

http://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf

-Lasse

 

[BobH]

On 09/04/2016 11:11 AM, John Larkin wrote:

I have a design that will use a DDS synthesizer to generate an
internal trigger rate for a pulse generator. The chip will be a ZYNQ
7020. The required upper frequency limit is maybe 20 MHz. The FPGA
will have the usual, 48 bit or so, phase accumulator and sine lookup
stuff clocked at maybe 100 MHz. The FPGA drives a fast DAC which in
turn drives an LC lowpass filter and a comparator. Standard stuff.

But could such a clock be generated entirely inside the FPGA?

Just using the MSB of the DDS phase accumulator works, but it will
have one full clock, 10 ns p-p, of jitter. That will be ugly at 20
MHz. I've got to look into some sort of outboard analog filtering to
clean up that single-bit clock, but I'm not optimistic. DDS is just
too weird.

Is the analog signal from your sine generator used elsewhere in the
system? If not, I don't see any advantage to using an external
asynchronous analog comparator on an analog signal. You will pick up at
least one clock cycle of jitter re-syncing the incoming analog signal to
the digital clock. Then you have the jitter from the delays out to the
DAC, the filter delays and the comparator jitter to add in.

If the digital logic for the timing generator is not in the same clock
domain as the system receiving it, you will pick up at least one clock
cycle of jitter in the clock boundary transition.

The only way I can think of to reduce the total jitter is the use as
fast a clock as you can, and keep everything in one clock domain. Then
you only have the clock source jitter that effects the entire system.

Good Luck,
BobH

 

[rickman]

On 9/5/2016 7:47 AM, Mike Perkins wrote:

On 05/09/2016 11:57, rickman wrote:
On 9/4/2016 3:13 PM, Mike Perkins wrote:
On 04/09/2016 19:11, John Larkin wrote:


I have a design that will use a DDS synthesizer to generate an
internal trigger rate for a pulse generator. The chip will be a ZYNQ
7020. The required upper frequency limit is maybe 20 MHz. The FPGA
will have the usual, 48 bit or so, phase accumulator and sine lookup
stuff clocked at maybe 100 MHz. The FPGA drives a fast DAC which in
turn drives an LC lowpass filter and a comparator. Standard stuff.

But could such a clock be generated entirely inside the FPGA?

Just using the MSB of the DDS phase accumulator works, but it will
have one full clock, 10 ns p-p, of jitter. That will be ugly at 20
MHz. I've got to look into some sort of outboard analog filtering to
clean up that single-bit clock, but I'm not optimistic. DDS is just
too weird.

Do you suppose that one of the FPGA PLLs be used to clean up the DDS
clock, scrub the jitter somehow? That could maybe be used over a
modest range, octave maybe, followed by some dividers.

That isn't how FPGA PLLs work. They add jitter rather than removing it!

Aren't you thinking of a digital PLL? The PLL in FPGAs is typically a
standard analog PLL and so *would* remove jitter.


Any other ideas for making a programmable-frequency clock with DDS
sort of resolution, but without all that outboard analog stuff?

I've been playing with sorta DDS in LT Spice, using a quantizer to
approximate the DDS accumulator and DAC, but that's obviously not the
best tool for this.

The jitter of a clock derived from within a FPGA would simply be related
to the clock frequency used.

If you use a 250MHz clock, as per the max frequency of many cheap FPGAs,
then jitter will be 4ns (+ a small bit).

Yes, you are clearly thinking of a digital PLL based on the digital
fabric of the FPGA. I assume John was talking about the dedicated PLLs
found in most FPGAS.

Most of my experience is with Xilinx who I don't believe use analogue PLLs.

Most FPGA PLLs are based on a variable length ring of gates which will
have jitter as gates are switched in and out of the loop.

Can you provide an example of a truly analogue PLL in a mainstream FPGA?

Xilinx uses a DLL, but I thought they also had a PLL capability.
Everyone else uses a PLL. Lattice data sheet for the XP2 says...

sysCLOCK™ PLLs
• Up to four analog PLLs per device
• Clock multiply, divide and phase shifting

Altera Cyclone V says this...

Phase-locked loops
(PLLs)
• Precision clock synthesis, clock delay compensation, and zero delay
buffering (ZDB)
• Integer mode and fractional mode

I don't think you can do zero delay buffering if the adjustment is
digital. Later in the document they say this...

• Jitter attenuation

and

PLL-based clock recovery Superior jitter tolerance

That's pretty compelling.

--

Rick C

 

[Allan Herriman]

On Mon, 05 Sep 2016 07:43:31 -0700, BobH wrote:

On 09/04/2016 11:11 AM, John Larkin wrote:


I have a design that will use a DDS synthesizer to generate an internal
trigger rate for a pulse generator. The chip will be a ZYNQ 7020. The
required upper frequency limit is maybe 20 MHz. The FPGA will have the
usual, 48 bit or so, phase accumulator and sine lookup stuff clocked at
maybe 100 MHz. The FPGA drives a fast DAC which in turn drives an LC
lowpass filter and a comparator. Standard stuff.

But could such a clock be generated entirely inside the FPGA?

Just using the MSB of the DDS phase accumulator works, but it will have
one full clock, 10 ns p-p, of jitter. That will be ugly at 20 MHz. I've
got to look into some sort of outboard analog filtering to clean up
that single-bit clock, but I'm not optimistic. DDS is just too weird.

Is the analog signal from your sine generator used elsewhere in the
system? If not, I don't see any advantage to using an external
asynchronous analog comparator on an analog signal. You will pick up at
least one clock cycle of jitter re-syncing the incoming analog signal to
the digital clock. Then you have the jitter from the delays out to the
DAC, the filter delays and the comparator jitter to add in.

If the digital logic for the timing generator is not in the same clock
domain as the system receiving it, you will pick up at least one clock
cycle of jitter in the clock boundary transition.

The only way I can think of to reduce the total jitter is the use as
fast a clock as you can, and keep everything in one clock domain. Then
you only have the clock source jitter that effects the entire system.

I had assumed that the pulse generator was outside the FPGA, and only the
trigger rate was being generated inside the FPGA. It's not quite clear
from the OP.


Allan

 

[Tim Wescott]

On Mon, 05 Sep 2016 07:43:31 -0700, BobH wrote:

On 09/04/2016 11:11 AM, John Larkin wrote:


I have a design that will use a DDS synthesizer to generate an internal
trigger rate for a pulse generator. The chip will be a ZYNQ 7020. The
required upper frequency limit is maybe 20 MHz. The FPGA will have the
usual, 48 bit or so, phase accumulator and sine lookup stuff clocked at
maybe 100 MHz. The FPGA drives a fast DAC which in turn drives an LC
lowpass filter and a comparator. Standard stuff.

But could such a clock be generated entirely inside the FPGA?

Just using the MSB of the DDS phase accumulator works, but it will have
one full clock, 10 ns p-p, of jitter. That will be ugly at 20 MHz. I've
got to look into some sort of outboard analog filtering to clean up
that single-bit clock, but I'm not optimistic. DDS is just too weird.

Is the analog signal from your sine generator used elsewhere in the
system? If not, I don't see any advantage to using an external
asynchronous analog comparator on an analog signal. You will pick up at
least one clock cycle of jitter re-syncing the incoming analog signal to
the digital clock. Then you have the jitter from the delays out to the
DAC, the filter delays and the comparator jitter to add in.

If the digital logic for the timing generator is not in the same clock
domain as the system receiving it, you will pick up at least one clock
cycle of jitter in the clock boundary transition.

The only way I can think of to reduce the total jitter is the use as
fast a clock as you can, and keep everything in one clock domain. Then
you only have the clock source jitter that effects the entire system.

Good Luck,
BobH

I can't speak to what John is doing, but if he needs a variable-frequency
pulse train with small jitter for some external purpose, then he needs
some sort of DDS or PLL technique.

Assuming that the FPGA clock is good and steady, one could get a finer
than one-clock resolution by playing tricks like using four or eight
output pins to a current DAC, which then charges a cap, which then feeds
a comparator. Then one wouldn't need to have a whole DDS inside -- but
one would still need some external analog stuff, and one would still need
to depend on the FPGA to have a nice consistent clock edge.

--

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

I'm looking for work -- see my website!

 

[rickman]

On 9/5/2016 1:15 PM, Tim Wescott wrote:

On Mon, 05 Sep 2016 07:43:31 -0700, BobH wrote:

On 09/04/2016 11:11 AM, John Larkin wrote:


I have a design that will use a DDS synthesizer to generate an internal
trigger rate for a pulse generator. The chip will be a ZYNQ 7020. The
required upper frequency limit is maybe 20 MHz. The FPGA will have the
usual, 48 bit or so, phase accumulator and sine lookup stuff clocked at
maybe 100 MHz. The FPGA drives a fast DAC which in turn drives an LC
lowpass filter and a comparator. Standard stuff.

But could such a clock be generated entirely inside the FPGA?

Just using the MSB of the DDS phase accumulator works, but it will have
one full clock, 10 ns p-p, of jitter. That will be ugly at 20 MHz. I've
got to look into some sort of outboard analog filtering to clean up
that single-bit clock, but I'm not optimistic. DDS is just too weird.

Is the analog signal from your sine generator used elsewhere in the
system? If not, I don't see any advantage to using an external
asynchronous analog comparator on an analog signal. You will pick up at
least one clock cycle of jitter re-syncing the incoming analog signal to
the digital clock. Then you have the jitter from the delays out to the
DAC, the filter delays and the comparator jitter to add in.

If the digital logic for the timing generator is not in the same clock
domain as the system receiving it, you will pick up at least one clock
cycle of jitter in the clock boundary transition.

The only way I can think of to reduce the total jitter is the use as
fast a clock as you can, and keep everything in one clock domain. Then
you only have the clock source jitter that effects the entire system.

Good Luck,
BobH

I can't speak to what John is doing, but if he needs a variable-frequency
pulse train with small jitter for some external purpose, then he needs
some sort of DDS or PLL technique.

Assuming that the FPGA clock is good and steady, one could get a finer
than one-clock resolution by playing tricks like using four or eight
output pins to a current DAC, which then charges a cap, which then feeds
a comparator. Then one wouldn't need to have a whole DDS inside -- but
one would still need some external analog stuff, and one would still need
to depend on the FPGA to have a nice consistent clock edge.

When you say "whole DDS", it's not that much circuitry. Besides, John
said he is using a 48 bit phase accumulator with a table lookup which
will give terrible phase jitter. A table lookup is a very poor choice
given the much better ways of high resolution phase to sine conversions
possible.

I'm not at all familiar with how you would control the current DAC if
you don't use a DDS. Are you suggesting the conversion of phase
directly to analog to create a sawtooth wave with the DAC? I don't
think you want to charge a cap. That would give a curved ramp sawtooth.
Maybe I'm not following at all.

I don't know the Zynq parts, but nearly all other FPGAs have proper
analog PLLs which will greatly reduce jitter. I believe the input
frequency range is somewhat limited, so there may need to be some extra
circuitry with the PLL to get the proper output frequency from the
acceptable input frequencies.

--

Rick C

 

[Rob Gaddi]

rickman wrote:

On 9/5/2016 7:47 AM, Mike Perkins wrote:
On 05/09/2016 11:57, rickman wrote:
On 9/4/2016 3:13 PM, Mike Perkins wrote:
On 04/09/2016 19:11, John Larkin wrote:


I have a design that will use a DDS synthesizer to generate an
internal trigger rate for a pulse generator. The chip will be a ZYNQ
7020. The required upper frequency limit is maybe 20 MHz. The FPGA
will have the usual, 48 bit or so, phase accumulator and sine lookup
stuff clocked at maybe 100 MHz. The FPGA drives a fast DAC which in
turn drives an LC lowpass filter and a comparator. Standard stuff.

But could such a clock be generated entirely inside the FPGA?

Just using the MSB of the DDS phase accumulator works, but it will
have one full clock, 10 ns p-p, of jitter. That will be ugly at 20
MHz. I've got to look into some sort of outboard analog filtering to
clean up that single-bit clock, but I'm not optimistic. DDS is just
too weird.

Do you suppose that one of the FPGA PLLs be used to clean up the DDS
clock, scrub the jitter somehow? That could maybe be used over a
modest range, octave maybe, followed by some dividers.

That isn't how FPGA PLLs work. They add jitter rather than removing it!

Aren't you thinking of a digital PLL? The PLL in FPGAs is typically a
standard analog PLL and so *would* remove jitter.


Any other ideas for making a programmable-frequency clock with DDS
sort of resolution, but without all that outboard analog stuff?

I've been playing with sorta DDS in LT Spice, using a quantizer to
approximate the DDS accumulator and DAC, but that's obviously not the
best tool for this.

The jitter of a clock derived from within a FPGA would simply be related
to the clock frequency used.

If you use a 250MHz clock, as per the max frequency of many cheap FPGAs,
then jitter will be 4ns (+ a small bit).

Yes, you are clearly thinking of a digital PLL based on the digital
fabric of the FPGA. I assume John was talking about the dedicated PLLs
found in most FPGAS.

Most of my experience is with Xilinx who I don't believe use analogue PLLs.

Most FPGA PLLs are based on a variable length ring of gates which will
have jitter as gates are switched in and out of the loop.

Can you provide an example of a truly analogue PLL in a mainstream FPGA?

Xilinx uses a DLL, but I thought they also had a PLL capability.
Everyone else uses a PLL. Lattice data sheet for the XP2 says...

sysCLOCK™ PLLs
• Up to four analog PLLs per device
• Clock multiply, divide and phase shifting

Altera Cyclone V says this...

Phase-locked loops
(PLLs)
• Precision clock synthesis, clock delay compensation, and zero delay
buffering (ZDB)
• Integer mode and fractional mode

I don't think you can do zero delay buffering if the adjustment is
digital. Later in the document they say this...

• Jitter attenuation

and

PLL-based clock recovery Superior jitter tolerance

That's pretty compelling.

The Cyclone series I at least know a thing about. There's an internal
octave VCO that you spin up to somewhere in to 600-1300 MHz range, and
then divide down. When I've looked at jitter performance a bit it's
fairly good; below the measurement floor of cheap measurement
equipment. I haven't really gone in with a spectrum analyzer to look
for spurs, but I'd imagine there's not much point to it. That probably
depends heavily on case-by-case power supply bypassing and exact
programmed frequency (as well as whether you're using an integer or
fractional divide) and is hard to talk about in any kind of general
sense.

The Zynq (at least according to the data sheet) does the same thing, VCO
in the 800-2100 MHz range and divide down.

Xilinx says nuttin' about the loop filter bandwidth, but Altera gives
typs for their three switchable filters as 0.3, 1.5, and 4 MHz.

--
Rob Gaddi, Highland Technology -- www.highlandtechnology.com
Email address domain is currently out of order. See above to fix.

 

Den tirsdag den 6. september 2016 kl. 19.50.23 UTC+2 skrev Rob Gaddi:

rickman wrote:

On 9/5/2016 7:47 AM, Mike Perkins wrote:
On 05/09/2016 11:57, rickman wrote:
On 9/4/2016 3:13 PM, Mike Perkins wrote:
On 04/09/2016 19:11, John Larkin wrote:


I have a design that will use a DDS synthesizer to generate an
internal trigger rate for a pulse generator. The chip will be a ZYNQ
7020. The required upper frequency limit is maybe 20 MHz. The FPGA
will have the usual, 48 bit or so, phase accumulator and sine lookup
stuff clocked at maybe 100 MHz. The FPGA drives a fast DAC which in
turn drives an LC lowpass filter and a comparator. Standard stuff.

But could such a clock be generated entirely inside the FPGA?

Just using the MSB of the DDS phase accumulator works, but it will
have one full clock, 10 ns p-p, of jitter. That will be ugly at 20
MHz. I've got to look into some sort of outboard analog filtering to
clean up that single-bit clock, but I'm not optimistic. DDS is just
too weird.

Do you suppose that one of the FPGA PLLs be used to clean up the DDS
clock, scrub the jitter somehow? That could maybe be used over a
modest range, octave maybe, followed by some dividers.

That isn't how FPGA PLLs work. They add jitter rather than removing it!

Aren't you thinking of a digital PLL? The PLL in FPGAs is typically a
standard analog PLL and so *would* remove jitter.


Any other ideas for making a programmable-frequency clock with DDS
sort of resolution, but without all that outboard analog stuff?

I've been playing with sorta DDS in LT Spice, using a quantizer to
approximate the DDS accumulator and DAC, but that's obviously not the
best tool for this.

The jitter of a clock derived from within a FPGA would simply be related
to the clock frequency used.

If you use a 250MHz clock, as per the max frequency of many cheap FPGAs,
then jitter will be 4ns (+ a small bit).

Yes, you are clearly thinking of a digital PLL based on the digital
fabric of the FPGA. I assume John was talking about the dedicated PLLs
found in most FPGAS.

Most of my experience is with Xilinx who I don't believe use analogue PLLs.

Most FPGA PLLs are based on a variable length ring of gates which will
have jitter as gates are switched in and out of the loop.

Can you provide an example of a truly analogue PLL in a mainstream FPGA?

Xilinx uses a DLL, but I thought they also had a PLL capability.
Everyone else uses a PLL. Lattice data sheet for the XP2 says...

sysCLOCK™ PLLs
• Up to four analog PLLs per device
• Clock multiply, divide and phase shifting

Altera Cyclone V says this...

Phase-locked loops
(PLLs)
• Precision clock synthesis, clock delay compensation, and zero delay
buffering (ZDB)
• Integer mode and fractional mode

I don't think you can do zero delay buffering if the adjustment is
digital. Later in the document they say this...

• Jitter attenuation

and

PLL-based clock recovery Superior jitter tolerance

That's pretty compelling.


The Cyclone series I at least know a thing about. There's an internal
octave VCO that you spin up to somewhere in to 600-1300 MHz range, and
then divide down. When I've looked at jitter performance a bit it's
fairly good; below the measurement floor of cheap measurement
equipment. I haven't really gone in with a spectrum analyzer to look
for spurs, but I'd imagine there's not much point to it. That probably
depends heavily on case-by-case power supply bypassing and exact
programmed frequency (as well as whether you're using an integer or
fractional divide) and is hard to talk about in any kind of general
sense.

The Zynq (at least according to the data sheet) does the same thing, VCO
in the 800-2100 MHz range and divide down.

Xilinx says nuttin' about the loop filter bandwidth, but Altera gives
typs for their three switchable filters as 0.3, 1.5, and 4 MHz.

Zynq datasheet say 1MHz and 4MHz

also says max input clock jitter 20% or 1ns

-Lasse

 

[Kevin Neilson]

On Sunday, September 4, 2016 at 12:11:40 PM UTC-6, John Larkin wrote:

I have a design that will use a DDS synthesizer to generate an
internal trigger rate for a pulse generator. The chip will be a ZYNQ
7020. The required upper frequency limit is maybe 20 MHz. The FPGA
will have the usual, 48 bit or so, phase accumulator and sine lookup
stuff clocked at maybe 100 MHz. The FPGA drives a fast DAC which in
turn drives an LC lowpass filter and a comparator. Standard stuff.

But could such a clock be generated entirely inside the FPGA?

You could use a single-bit DAC (like a Sigma-Delta DAC) filtered by a 1-pole RC filter and then run back into an LVDS input. So then you'd just have the RC filter external. But I don't know if the oversampling rate (100MHz/20MHz) is enough precision.

Another option is to use the lower bits of your phase accumulator to add phase to the output using the ODELAY blocks. You can get a precision of 78ps if you use 200MHz as your reference clock. However, I'm not certain how often you can update the ODELAY delay value.

 

[John Larkin]

On Sun, 04 Sep 2016 11:11:32 -0700, John Larkin
<jjlarkin@highlandtechnology.com> wrote:

I have a design that will use a DDS synthesizer to generate an
internal trigger rate for a pulse generator. The chip will be a ZYNQ
7020. The required upper frequency limit is maybe 20 MHz. The FPGA
will have the usual, 48 bit or so, phase accumulator and sine lookup
stuff clocked at maybe 100 MHz. The FPGA drives a fast DAC which in
turn drives an LC lowpass filter and a comparator. Standard stuff.

But could such a clock be generated entirely inside the FPGA?

Just using the MSB of the DDS phase accumulator works, but it will
have one full clock, 10 ns p-p, of jitter. That will be ugly at 20
MHz. I've got to look into some sort of outboard analog filtering to
clean up that single-bit clock, but I'm not optimistic. DDS is just
too weird.

Do you suppose that one of the FPGA PLLs be used to clean up the DDS
clock, scrub the jitter somehow? That could maybe be used over a
modest range, octave maybe, followed by some dividers.

Any other ideas for making a programmable-frequency clock with DDS
sort of resolution, but without all that outboard analog stuff?

I've been playing with sorta DDS in LT Spice, using a quantizer to
approximate the DDS accumulator and DAC, but that's obviously not the
best tool for this.

Well, it's looking like I'll just use an external DDS chip, AD9835
probably, with the usual LC lowpass filter and comparator. I can clock
that from a handy 50 MHz oscillator that we need for the Ethernet phy.

Looks like trying to do this inside the FPGA is too risky, jitter and
such. That close to Nyquist, I will need a good filter.




--

John Larkin Highland Technology, Inc
picosecond timing precision measurement

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com