Elegant way to shift replace

Hi,

I'm looking for an elegant way to do the following. Any ideas welcome:

Inputs:
-In (6 bits)
-temp (2 bits)

Outputs:
-Out (10 bits)

Objective:
Out[temp+5:temp] = In
The other bits of Out should be untouched (should have original values).

Thanks.

 

[GaborSzakacs]

kgbenator@gmail.com wrote:

Hi,

I'm looking for an elegant way to do the following. Any ideas welcome:

Inputs:
-In (6 bits)
-temp (2 bits)

Outputs:
-Out (10 bits)

Objective:
Out[temp+5:temp] = In
The other bits of Out should be untouched (should have original values).

Thanks.

As you would find if you tried your code as is,
this is not supported in Verilog, however you
can write:

Out[temp +: 6] = In;

and get the equivalent.

Or you could use shift operators as if you were writing in C:

Out = Out & ~(6'h3F << temp) | (In << temp);

--
Gabor

 

[Kevin Neilson]

Sounds like a general-purpose barrel shifter:

assign out = in << temp;

or

assign out = in * 2**temp;
You say "the other bits of Out should be untouched", but that would imply a latch, and I'm not really sure you'd want that. Is there a clock?

 

= In;

Interesting, thanks!

On Monday, May 13, 2013 7:55:01 AM UTC-7, gabor wrote:

kgbenator@gmail.com wrote:

Hi,



I'm looking for an elegant way to do the following. Any ideas welcome:



Inputs:

-In (6 bits)

-temp (2 bits)



Outputs:

-Out (10 bits)



Objective:

Out[temp+5:temp] = In

The other bits of Out should be untouched (should have original values).



Thanks.



As you would find if you tried your code as is,

this is not supported in Verilog, however you

can write:



Out[temp +: 6] = In;



and get the equivalent.



Or you could use shift operators as if you were writing in C:



Out = Out & ~(6'h3F << temp) | (In << temp);



--

Gabor