EE: PWM Amplifier Load Equalization

[Chris Carlen]

Hi:

I am designing a PWM amplifier based on an APEX SA60 device to put up to
5A peak into a solenoid load of 2.55ohms + 260uH. I have modeled it in
SPICE, and it works fine. I'm using a 100kHz switching frequency. I
set my LC output filters at 10kHz cutoff, so they are 27uH + 8.2uF.

The APEX datasheet recommends using an equalization network to cancel
the inductive component of the load. So that works out to 2.55ohms +
40uF. Obviously, things don't work very well without this, as there
would be tremendous peaking just before the filters roll off.

The 8.2uF filter caps are a tolerable pair of Panasonic ECQ-E(F)
metalized polyesters that can handle 4A ripple at up to 100kHz. They
will see about 2.3A RMS under worst case conditions of 10kHz sustained
12.75V peak output (that voltage would generate 5A into the load at
lower frequencies).

The equalization cap however sees 2.9A. With its 40uF capacitance,
there are few choices of cap that can tolerate this, except for perhaps
4 parallel ECQ-E(F) series 10uF caps. Electrolytic caps are out of the
question at this low of a capacitance.

The nice thing about the equalization network is that is simplifies the
feedback loop design. Since the voltage monitoring is done right at the
PWM FETs, there is negligible phase shift from the power electronics.
Thus, a simple integrator can be used with little effort at AC modeling
needed.

However, if I wanted to get rid of the equalization network in order to
eliminate the need for its bulky capacitors, then I would have to sense
the voltage at the post-filter output terminals. This would require a
more careful feedback loop design and modeling, which I suppose could be
tuned to keep things stable by undoing the peaking in the absence of the
equalizer.

My question is thus: What is done in most PWM amps? Do they attempt to
resistify the load with an equalization network, or design a more
complex feedback loop that stabilize the amplifier while sensing the
actual load voltage after the filters?

Thanks for input.


Good day!


--
_______________________________________________________________________
Christopher R. Carlen
Principal Laser/Optical Technologist
Sandia National Laboratories CA USA
crcarle@sandia.gov -- NOTE: Remove "BOGUS" from email address to reply.

 

[Terry Given]

Chris Carlen wrote:

Hi:

I am designing a PWM amplifier based on an APEX SA60 device to put up to
5A peak into a solenoid load of 2.55ohms + 260uH. I have modeled it in
SPICE, and it works fine. I'm using a 100kHz switching frequency. I
set my LC output filters at 10kHz cutoff, so they are 27uH + 8.2uF.

The APEX datasheet recommends using an equalization network to cancel
the inductive component of the load. So that works out to 2.55ohms +
40uF. Obviously, things don't work very well without this, as there
would be tremendous peaking just before the filters roll off.

The 8.2uF filter caps are a tolerable pair of Panasonic ECQ-E(F)
metalized polyesters that can handle 4A ripple at up to 100kHz. They
will see about 2.3A RMS under worst case conditions of 10kHz sustained
12.75V peak output (that voltage would generate 5A into the load at
lower frequencies).

The equalization cap however sees 2.9A. With its 40uF capacitance,
there are few choices of cap that can tolerate this, except for perhaps
4 parallel ECQ-E(F) series 10uF caps. Electrolytic caps are out of the
question at this low of a capacitance.

The nice thing about the equalization network is that is simplifies the
feedback loop design. Since the voltage monitoring is done right at the
PWM FETs, there is negligible phase shift from the power electronics.
Thus, a simple integrator can be used with little effort at AC modeling
needed.

However, if I wanted to get rid of the equalization network in order to
eliminate the need for its bulky capacitors, then I would have to sense
the voltage at the post-filter output terminals. This would require a
more careful feedback loop design and modeling, which I suppose could be
tuned to keep things stable by undoing the peaking in the absence of the
equalizer.

My question is thus: What is done in most PWM amps? Do they attempt to
resistify the load with an equalization network, or design a more
complex feedback loop that stabilize the amplifier while sensing the
actual load voltage after the filters?

Thanks for input.


Good day!

Hi Chris,

I presume by "equalisation network" you are talking about a parallel RC
damper across the 8.2uF. the general ROT is 3xC in series with R=Zo. I
had a read of an32, and spiced the conjugate matching network. Sure
enough, it tames the evil filter resonance.

the general ROT for RC damping an LC filter is to use Cdamp = 3*Cfilter,
Rdamp = sqrt(Lfilter/Cfilter) giving 1.8R and 24uF, placed across
Cfilter. spice shows this to behave in a similar manner to the conjugate
damping network (only looking at ac response)

another, albeit less common technique, is RL damping across the filter
inductor. The ROT is Ldamp = Lfilter/3 and Rdamp = sqrt(Lfilter/Cfilter)
ie 1.8R and 9uH or so. again, spice shows this to be quite effective. I
have used LR damping quite a bit in inverter circuits, where 50/60Hz
current thru Cdamp cooks Rdamp.

Cheers
Terry