EDK Modelsim Behavioral Simulation Error

[hansman]

I am trying to build and simulate an FPGA System built with
EDK 6.1.1. The system contains a PPC and an Ethernet MAC.

I have set up the simulation libraries according to the getting started with edk manual.

when compiling the behavioral simulation (do system.do) modelsim 5.7g puts following errors:

If one of you knows the answer for this behavior it would be great!


# Model Technology ModelSim SE vcom 5.7g Compiler 2003.10 Oct 10 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package plb2opb_bridge_pkg
# -- Loading package proc_common_pkg
# -- Compiling entity plb2opb_bridge_opb_if
# -- Compiling architecture plb2opb_bridge_opb_if of plb2opb_bridge_opb_if
# WARNING[1]: C:/Xilinx/EDK/hw/XilinxProcessorIPLib/pcores/plb2opb_bridge_v1_00_b/hdl/vhdl/plb2opb_bridge_opb_if.vhd(296): No default binding for component: "bgo_opb_if_ila". (No entity named "bgo_opb_if_ila" was found)
# WARNING[1]: C:/Xilinx/EDK/hw/XilinxProcessorIPLib/pcores/plb2opb_bridge_v1_00_b/hdl/vhdl/plb2opb_bridge_opb_if.vhd(302): No default binding for component: "bgo_opb_if". (No entity named "bgo_opb_if" was found)

and

Model Technology ModelSim SE vcom 5.7g Compiler 2003.10 Oct 10 2003
# -- Loading package standard
# ** Error: C:/Xilinx/EDK/hw/XilinxProcessorIPLib/pcores/lib_common_v1_00_a/hdl/vhdl/addr_iet_inc_ip_bus.vhd(1): near "xlxv35eb": syntax error
# WARNING[4]: C:/Xilinx/EDK/hw/XilinxProcessorIPLib/pcores/lib_common_v1_00_a/hdl/vhdl/addr_iet_inc_ip_bus.vhd(1): A space is required between a number and an identifier.
# WARNING[4]: C:/Xilinx/EDK/hw/XilinxProcessorIPLib/pcores/lib_common_v1_00_a/hdl/vhdl/addr_iet_inc_ip_bus.vhd(1): A space is required between a number and an identifier.
# ** Error: C:/Xilinx/EDK/hw/XilinxProcessorIPLib/pcores/lib_common_v1_00_a/hdl/vhdl/addr_iet_inc_ip_bus.vhd(1): near "ţî_": Identifier may not end with an underscore.
# WARNING[4]: C:/Xilinx/EDK/hw/XilinxProcessorIPLib/pcores/lib_common_v1_00_a/hdl/vhdl/addr_iet_inc_ip_bus.vhd(1): A space is required between a number and an identifier.
# ** Error: C:/Xilinx/EDK/hw/XilinxProcessorIPLib/pcores/lib_common_v1_00_a/hdl/vhdl/addr_iet_inc_ip_bus.vhd(1): near "@Ž": unterminated string
# ** Error: C:/Xilinx/EDK/hw/XilinxProcessorIPLib/pcores/lib_common_v1_00_a/hdl/vhdl/addr_iet_inc_ip_bus.vhd(2): near "n": unterminated string
# WARNING[4]: C:/Xilinx/EDK/hw/XilinxProcessorIPLib/pcores/lib_common_v1_00_a/hdl/vhdl/addr_iet_inc_ip_bus.vhd(4): A space is required between a number and an identifier.
# WARNING[4]: C:/Xilinx/EDK/hw/XilinxProcessorIPLib/pcores/lib_common_v1_00_a/hdl/vhdl/addr_iet_inc_ip_bus.vhd(4): A space is required between a number and an identifier.
# ** Error: C:/Xilinx/EDK/hw/XilinxProcessorIPLib/pcores/lib_common_v1_00_a/hdl/vhdl/addr_iet_inc_ip_bus.vhd(6): near "e_": Identifier may not end with an underscore.
# ** Error: C:/Xilinx/EDK/hw/XilinxProcessorIPLib/pcores/lib_common_v1_00_a/hdl/vhdl/addr_iet_inc_ip_bus.vhd(6): unterminated string
# ** Error: C:/Xilinx/EDK/hw/XilinxProcessorIPLib/pcores/lib_common_v1_00_a/hdl/vhdl/addr_iet_inc_ip_bus.vhd(7): unterminated string
# WARNING: C:/Xilinx/EDK/hw/XilinxProcessorIPLib/pcores/lib_common_v1_00_a/hdl/vhdl/addr_iet_inc_ip_bus.vhd(8): Non-printable characters are not allowed in extended identifiers
# ERROR: C:/Modeltech_5.7g/win32/vcom failed.
# Error in macro ./system.do line 140
# C:/Modeltech_5.7g/win32/vcom failed.
# while executing
# "vcom -93 -work lib_common_v1_00_a C:/Xilinx/EDK/hw/XilinxProcessorIPLib/pcores/lib_common_v1_00_a/hdl/vhdl/addr_iet_inc_ip_bus.vhd
# "

 

[Jonathan Bromley]

"hansman" <johann.waldherr@mediornet.com> wrote in message
news:c300168c343f812dd46fedeffd8d6fe7@localhost.talkaboutprogramming.com...

modelsim 5.7g puts following errors:

# WARNING[1]: [...]:
No default binding for component: "bgo_opb_if_ila".

(No entity named "bgo_opb_if_ila" was found)

It's only a warning. When compiling the component instantiation, ModelSim
tries to find a matching entity in the library. Ignore this.

(1): near "xlxv35eb": syntax error

Means you have done something pretty stupid: a missing semicolon,
or the wrong sort of brackets, or something goofy like that.

A space is required between a number and an
identifier.

Usually happens when you try to write a time like "10ns" instead of "10 ns".
This is a nice clear error message, surely?

: Identifier may not end with an underscore.

Which part of that do you not understand?

: near "@Ž": unterminated string

The junk characters here suggest either that your text editor is allowing
you to include accented or other non-ASCII characters, or that
you are trying to compile a binary file.

# WARNING: Non-printable characters are not allowed in extended
identifiers

Same thing. An "extended identifier" is a name enclosed in backslashes
so that it can include characters other than alphanumerics. A feature
much used by automatic VHDL-generating tools like netlisters.


Check to see that you have not somehow tried to compile something that
is not VHDL source code - some of these error messages look pretty wild.
--

Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[hansman]

Hi,

Thanks for the info.

the problem is that the sources are ENCRYPTED VHDL provided by Xilinx EDK. Seems that the seed for the VHDL encryption files does not correctly decrypt them.

Am only I encountering such problems? I will try different modelsim versions as next step.

greets
Hans

 

[hansman]

Hi, thanks.

The problem is that the syntax errors are resulting from files that are delivered by Xilinx in encrypted VHDL! So I have almost no means to check the source of the problem.

I wonder if only I am encountering this sort of problem. Maybe it's an setup problem of modelsim/EDK?

greets
hans