EDK 6.2 ISE verilog toplevel possible ?

A

Antti Lukats

Guest
Hi

does anybody know if it is possible to use EDK system in ISE toplevel if the
toplevel is in verilog?
So far ISE/EDK mixed language support has been always towards VHDL, in last
releases the mixed language support is defenetly better but we still have
some problem with some mixed designs.

so simple question:
ISE toplevel (verilog)
includes a EDK system, all seems to be OK, but synthesis says that the
system module is not found.

any workaround, hint what todo? wait for next service pack ???


Antti
 
This seems to be a bug in projnav when using the XMP as a source file.

ISE creates the EDK project in VHDL mode. This has to be changed.
The only way to do that today is to open the xmp file in an editor
and change VHDL to VERILOG.

Basically the projnav could not resolve the path to the edk data from
the xmp. One way around this is to generate the netlist in XPS and
then take that system.v file and instantiate it as a source
in projnav. You will need to remove the xmp as a source.

Antti Lukats wrote:
Hi

does anybody know if it is possible to use EDK system in ISE toplevel if the
toplevel is in verilog?
So far ISE/EDK mixed language support has been always towards VHDL, in last
releases the mixed language support is defenetly better but we still have
some problem with some mixed designs.

so simple question:
ISE toplevel (verilog)
includes a EDK system, all seems to be OK, but synthesis says that the
system module is not found.

any workaround, hint what todo? wait for next service pack ???


Antti
Click to expand...

--
/ 7\'7 Paulo Dutra (paulo.dutra@xilinx.com)
\ \ ` Xilinx hotline@xilinx.com
/ / 2100 Logic Drive http://www.xilinx.com
\_\/.\ San Jose, California 95124-3450 USA
 
"Paulo Dutra" <paulo.dutra@NOSPAM.com> wrote in message
news:40D8C416.8060607@NOSPAM.com...
This seems to be a bug in projnav when using the XMP as a source file.

ISE creates the EDK project in VHDL mode. This has to be changed.
The only way to do that today is to open the xmp file in an editor
and change VHDL to VERILOG.

Basically the projnav could not resolve the path to the edk data from
the xmp. One way around this is to generate the netlist in XPS and
then take that system.v file and instantiate it as a source
in projnav. You will need to remove the xmp as a source.

Antti Lukats wrote:
Hi

does anybody know if it is possible to use EDK system in ISE toplevel if
the
toplevel is in verilog?
Click to expand...
Thanks Paulo,

well unfortunatly if I remove the .XMP from project I can not do "update
sources" any more from Project Navigator!
so the fix is not a real solution! :( Any ideas when/which service pack will
fix this problem??

ISE/EDK integration is getting better, but would be real nice to see it
working one day !!
(before doom-day hopefully!)

Antti
 
Antti,
Did you try goign to EDK and doign an Tools-> Export To ProjNav. This
will create a new ProjNav project for you after runnign synthesis for
EDK subsystem. Remember to go to Project Options and select

* This is submodule of my design
* Implementation Flow: ISE

Once the new projnav project is created, you can add your own files
there. If there are any chagnes in EDK, you can re-export from EDK to
the existing ProjNav project.

Amit.

Antti Lukats wrote:

"Paulo Dutra" <paulo.dutra@NOSPAM.com> wrote in message
news:40D8C416.8060607@NOSPAM.com...

This seems to be a bug in projnav when using the XMP as a source file.

ISE creates the EDK project in VHDL mode. This has to be changed.
The only way to do that today is to open the xmp file in an editor
and change VHDL to VERILOG.

Basically the projnav could not resolve the path to the edk data from
the xmp. One way around this is to generate the netlist in XPS and
then take that system.v file and instantiate it as a source
in projnav. You will need to remove the xmp as a source.

Antti Lukats wrote:

Hi

does anybody know if it is possible to use EDK system in ISE toplevel if

the

toplevel is in verilog?


Thanks Paulo,

well unfortunatly if I remove the .XMP from project I can not do "update
sources" any more from Project Navigator!
so the fix is not a real solution! :( Any ideas when/which service pack will
fix this problem??

ISE/EDK integration is getting better, but would be real nice to see it
working one day !!
(before doom-day hopefully!)

Antti
Click to expand...
 
"Amit Kasat" <Amit.Kasat@nospam-xilinx.com> wrote in message
news:40D9B833.1040304@nospam-xilinx.com...
Antti,
Did you try goign to EDK and doign an Tools-> Export To ProjNav. This
will create a new ProjNav project for you after runnign synthesis for
EDK subsystem. Remember to go to Project Options and select

* This is submodule of my design
* Implementation Flow: ISE

Once the new projnav project is created, you can add your own files
there. If there are any chagnes in EDK, you can re-export from EDK to
the existing ProjNav project.

Amit.
Click to expand...
Thanks, but I can add system.xmp to the ISE project and everything works
100% fine as long as the toplevel ISE project is VHDL.
In case of verilog toplevel synthesis stops on error module not found.

If I add system.v (not system.xmp) to the ISE project I can not update the
MicroBlaze sources from ISE project !!

So there is no solution so far :(
hope some next EDK service packs solves the problem!

Antti
 
"Paulo Dutra" <paulo.dutra@NOSPAM.com> wrote in message
news:40D8C416.8060607@NOSPAM.com...
This seems to be a bug in projnav when using the XMP as a source file.

ISE creates the EDK project in VHDL mode. This has to be changed.
The only way to do that today is to open the xmp file in an editor
and change VHDL to VERILOG.

Basically the projnav could not resolve the path to the edk data from
the xmp. One way around this is to generate the netlist in XPS and
then take that system.v file and instantiate it as a source
in projnav. You will need to remove the xmp as a source.
--
/ 7\'7 Paulo Dutra (paulo.dutra@xilinx.com)
\ \ ` Xilinx hotline@xilinx.com
/ / 2100 Logic Drive http://www.xilinx.com
\_\/.\ San Jose, California 95124-3450 USA
Click to expand...
Dear Paulo!

there is exists a real workaround that allows normal flow in ISE having a
verilog toplevel and system.xmp !
http://xilinx.openchip.org
the fix is posted there :)

Antti Lukats,
who would accept paypal donations to antti@case2000.com email address to
help me to post more real fixes and hints where Xilinx hotline fails to help
;)

kidding, I am just an unemployed FPGA-guru living in foreign country far
away from home who hopes this "ISE/EDK verilog top" hint is useful to some
one at least!

And to Xilinx: I have fighted months and monhts with ISE/EDK/V2PDK bugs, its
getting better all the time, but still has some gotchas that may make the
use of the tools a real frustration for those who just obtain the SW and try
to use it.
 
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