EDK 6.1: User Logic

[Joe]

Hello, <p>I am trying to add user logic to an EDK project. I have tried attching to both the OPB and PLB busses using the ssp0 reference designs. I have striped down the user logic portion of the reference designs to be like a RAM that I can write to /read from. I can download the design to the development board, but the data that I read back is garbage. <p>In the MHS file for the core, I have: <BR>
BEGIN plb_simple_core <BR>
&amp;nbsp;PARAMETER INSTANCE = plb_simple_core_0 <BR>
&amp;nbsp;PARAMETER C_BASEADDR = 0xD0000000 <BR>
&amp;nbsp;PARAMETER C_HIGHADDR = 0xD000FFFF <BR>
&amp;nbsp;PARAMETER c_mir_baseaddr = 0xD0010100 <BR>
&amp;nbsp;PARAMETER c_mir_highaddr = 0xD00101FF <BR>
&amp;nbsp;BUS_INTERFACE SPLB = plb <BR>
&amp;nbsp;PORT plb_clk = sys_clk <BR>
END <p>And in the C code I have: <BR>
#define CORE_ADDR XPAR_PLB_SIMPLE_CORE_0_BASEADDR <p>Xuint32 reg_0; <p>// Write data to core <BR>
XIut32( (CORE_ADDR + 0x0000), 0x00000000); // or some other data <p>// Read data from core <BR>
reg_0 = XIo_In32((CORE_ADDR + 0x0000)); <BR>
xil_printf("Data at address 0 is: %d \r\n", reg_0); <p>Is this the correct method for reading/writing to the core? <p>If so any idea where else my error could be? <p>Thanks, <BR>
Joe

 

[Amit Kasat]

The C-code you are referring to appear to be from Xilinx drivers. Did
you modify the driver for your own IP. Also, what driver have you
assigned to this IP in the MSS file.

Amit.

Joe wrote:

Hello,

I am trying to add user logic to an EDK project. I have tried attching
to both the OPB and PLB busses using the ssp0 reference designs. I have
striped down the user logic portion of the reference designs to be like
a RAM that I can write to /read from. I can download the design to the
development board, but the data that I read back is garbage.

In the MHS file for the core, I have:
BEGIN plb_simple_core
PARAMETER INSTANCE = plb_simple_core_0
PARAMETER C_BASEADDR = 0xD0000000
PARAMETER C_HIGHADDR = 0xD000FFFF
PARAMETER c_mir_baseaddr = 0xD0010100
PARAMETER c_mir_highaddr = 0xD00101FF
BUS_INTERFACE SPLB = plb
PORT plb_clk = sys_clk
END

And in the C code I have:
#define CORE_ADDR XPAR_PLB_SIMPLE_CORE_0_BASEADDR

Xuint32 reg_0;

// Write data to core
XIut32( (CORE_ADDR + 0x0000), 0x00000000); // or some other data

// Read data from core
reg_0 = XIo_In32((CORE_ADDR + 0x0000));
xil_printf("Data at address 0 is: %d \r\n", reg_0);

Is this the correct method for reading/writing to the core?

If so any idea where else my error could be?

Thanks,
Joe

 

[qudhs]

Hi!
from the manual given along with the reference design, it seems you
should use the C_BASEADDR to access user logic. I think your code should
work if you change the CORE_ADDR macro definition to C_BASE_ADDR.
#define CORE_ADDR C_BASE_ADDR
--yang

Joe wrote:

Hello,

I am trying to add user logic to an EDK project. I have tried attching
to both the OPB and PLB busses using the ssp0 reference designs. I
have striped down the user logic portion of the reference designs to
be like a RAM that I can write to /read from. I can download the
design to the development board, but the data that I read back is
garbage.

In the MHS file for the core, I have:
BEGIN plb_simple_core
PARAMETER INSTANCE = plb_simple_core_0
PARAMETER C_BASEADDR = 0xD0000000
PARAMETER C_HIGHADDR = 0xD000FFFF
PARAMETER c_mir_baseaddr = 0xD0010100
PARAMETER c_mir_highaddr = 0xD00101FF
BUS_INTERFACE SPLB = plb
PORT plb_clk = sys_clk
END

And in the C code I have:
#define CORE_ADDR XPAR_PLB_SIMPLE_CORE_0_BASEADDR

Xuint32 reg_0;

// Write data to core
XIut32( (CORE_ADDR + 0x0000), 0x00000000); // or some other data

// Read data from core
reg_0 = XIo_In32((CORE_ADDR + 0x0000));
xil_printf("Data at address 0 is: %d \r\n", reg_0);

Is this the correct method for reading/writing to the core?

If so any idea where else my error could be?

Thanks,
Joe

 

[joe]

Thanks for the replies Amit and Yang. <p>I solved the problem myself though - it was in my VHDL code. I wasn't taking into account that bit 30 and 31 of Bus2IP_Addr were being dropped. Now it is working as expected. <p>Thanks, <BR>
Joe