EDIF netlist access in Xilinx ISE 8.1i

[Jahanzebanwer]

I am using Xilinx Project Navigator ISE 8.1i. I want to access the EDI
netlist of my program which is write as a behavioral verilog code. Suppos
I write the code (a+b), than I could see in the RTL and Technolog
schematics that a full-adder has been created inside a LUT but i want t
access the EDIF netlist of this RTL diagram created by XIlinx.
Moreover, I learned in the Xilinx Development Reference Guide that the NG
netlist is a logical description of the circuit whereas the NGD netlis
Xilinx created for my programs are totally vague. It seems like it is base
on the local primitives of the xilinx board but atleast no logica
description is available.
Thanks for your time.



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[Petter Gustad]

"Jahanzebanwer" <jahanzebanwer2002@n_o_s_p_a_m.gmail.com> writes:

I am using Xilinx Project Navigator ISE 8.1i. I want to access the EDIF

Your installation might contain the program ngc2edif which can be used
to convert from the Xilinx netlist format to EDIF.

Petter
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