Edge Detection

[Ben Heard]

comp.lang.verilog,

I need to detect an edge for an interrupt routine. A temperature
sensor drives a line low upon reaching a critical stage. Once the heat
source is removed, the line returns high. I would like to detect each
edge and interrupt a processor. The chain of events would be to detect
the edge going low and interrupts the processor (drives proc_int low).
The processor then clears the interrupt (returning proc_int high). When
the heat source is removed and the interrupt line returns high I want to
interrupt the processor again (drive proc_int low).

All of this is to be done in a Xilinx Coolrunner-II CPLD. Here is the
example source that I have been trying to compile.

module edgeDetect(
clock,
reset_n,
clear_int,
temp,
proc_int
);

input clock;
input reset_n;
input clear_int;
input temp;
output proc_int;

reg proc_int;

always @( posedge temp or negedge temp )
begin
proc_int <= 1'b0;
end

always @( posedge clock )
begin
if( !reset_n || clear_int )
proc_int <= 1'b1;
end

endmodule

The trouble is that the synthesis tool is unable to synthesize this
and spits back the error that a "Multi-source in Unit <edgeDetect> on
signal <proc_int> not replaced by logic[.] Signal is stuck at GND[.]"

Is there something inherently wrong with what I'm trying to do here?

Thanks,
Ben

 

[nospam]

Ben Heard <BenH@cipheroptics.com> wrote:

Is there something inherently wrong with what I'm trying to do here?

Yes edge events are synthesised into flipflops and your parts (and all
others that I know) don't have flipflops clocked on both edges.

You seem to have a system clock. Register your input with the clock to
synchronise it then register it again to produce a delayed version. xor the
output of both registers to produce a well defined one clock pulse for
each change of input state. With you interrupt latch it should fit in 3
cells of the CPLD.

 

[VhdlCohen]

module edgeDetect(
clock,
reset_n,
clear_int,
temp,
proc_int
);

input clock;
input reset_n;
input clear_int;
input temp;
output proc_int;

reg proc_int;

always @( posedge temp or negedge temp )
begin
proc_int <= 1'b0;
end

always @( posedge clock )
begin
if( !reset_n || clear_int )
proc_int <= 1'b1;
end

endmodule

The trouble is that the synthesis tool is unable to synthesize this
and spits back the error that a "Multi-source in Unit <edgeDetect> on
signal <proc_int> not replaced by logic[.] Signal is stuck at GND[.]"

Is there something inherently wrong with what I'm trying to do here?

Proc_int is driven by two separate blocks.
A solution:
1. reclock temp with 2 FF for metastability.
2. Use clock.
3. DO edge detect thru 1-shot
always @( posedge clock or negedge reset)
begin
if (!reset) begin
temp1 <= 1'b0; temp2 <= 1'b0; temp3 <= 1'b0;
end
else begin
temp1 <= temp;
temp2 <= temp1;
temp3 <= temp2;
// temp2 0 0 0 1 1 1 1 1
// temp3 0 0 0 0 1 1 1 1
if( !reset_n & temp2 & !temp3)
proc_int <= 1'b1;
end
Anyway, that's the idea -- 1 clock!
----------------------------------------------------------------------------
Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
http://www.vhdlcohen.com/ vhdlcohen@aol.com
Author of following textbooks:
* Using PSL/SUGAR with Verilog and VHDL
Guide to Property Specification Language for ABV, 2003 isbn 0-9705394-4-4
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
0-9705394-2-8
* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
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