Edge Detection circuit.

[Raghavendra]

Hi all,
Flip flop differs from a latch because of edge detection
circuit.How edge detection circuit is implemented.
Regards
Raghavendra.Sortur

 

[Guitarman]

raghurash@rediffmail.com (Raghavendra) wrote in message news:<1776d39.0410072144.69a98c53@posting.google.com>...

Hi all,
Flip flop differs from a latch because of edge detection
circuit.How edge detection circuit is implemented.
Regards
Raghavendra.Sortur

Here is a Process that finds the rising edge of YOUR_SIG signal

-- This process is used to find the rising edge of the YOUR_SIG
Edge_find: process (CLK_IN,RESET_IN)
begin
if RESET_IN ='1' then -- Async Reset
YOUR_SIG_FILTER <= "00000000";
YOUR_SIG_EDGE <= '0';
elsif rising_edge (CLK_IN) then
-- Detects rising Edge of YOUR_SIG
if YOUR_SIG_FILTER = "11110000" then
YOUR_SIG_EDGE <= '1';
else
YOUR_SIG_EDGE <= '0';
end if;
--Shifts in new input values into filter
YOUR_SIG_FILTER(7 downto 0) <= YOUR_SIG & YOUR_SIG_FILTER(7 downto
1);
end if;
end process;

When YOUR_SIG_EDGE is '1' then you have a rising edge. I used the 8
bit registar as a filter. You wouldn't have to use the 8 bits a single
signal would work.

 

[Eric Smith]

Raghavendra wrote:

Flip flop differs from a latch because of edge detection
circuit.How edge detection circuit is implemented.

Paul Uiterlinden <no@spam.nl> writes:

By two latches in succesion, the first has an active low enable
(transparant while its enable is low), the second active high. These
two latches form a so called master-slave pair.

That's how the pulse-triggered flip-flops worked, but that technique has
not been in common use for a long time. It is not truly edge-sensitive,
because it is sensitive to input changes during the entire low period of
the clock, not just a narrow window near the rising edge.

One of the earliest true edge-triggered D flip-flops was the SN7474.
There's a logic diagram at the bottom right of the first page of the
TI data sheet, which can be found here:
http://focus.ti.com/docs/prod/folders/print/sn7474.html

It's a little tricky to understand; it is helpful to redraw the
logic diagram with the asynchronous preset and clear inputs omitted.
I haven't found any good written description of how it works, but
there's probably one in a digital design textbook somewhere.

An example of an edge-triggered J-K/ flip-flop is the SN74109. There's
a logic diagram in its data sheet as well.

 

[Ken Smith]

In article <416755D1.4AF40F94@yahoo.com>, rickman <john@bluepal.net> wrote:

Eric Smith wrote:

Raghavendra wrote:
Flip flop differs from a latch because of edge detection
circuit.How edge detection circuit is implemented.

Paul Uiterlinden <no@spam.nl> writes:
By two latches in succesion, the first has an active low enable
(transparant while its enable is low), the second active high. These
two latches form a so called master-slave pair.

That's how the pulse-triggered flip-flops worked, but that technique has
not been in common use for a long time. It is not truly edge-sensitive,
because it is sensitive to input changes during the entire low period of
the clock, not just a narrow window near the rising edge.

I'm not clear why you say it is "sensitive" to input changes in the low
clock period. The input can change many times while the clock is low,
but only the last state of the input before the clock rises will be
remembered by the first latch and therefore by the second latch which is
the output.

He just didn't read your post carefully. You are right about how it
works.

--
--
kensmith@rahul.net forging knowledge

 

[Pieter Hulshoff]

Eric Smith wrote:

That's how the pulse-triggered flip-flops worked, but that technique has
not been in common use for a long time. It is not truly edge-sensitive,
because it is sensitive to input changes during the entire low period of
the clock, not just a narrow window near the rising edge.

Could we please all use the same terminology? A pulse (level) triggered
memory device is usually called a latch. An edge triggered memory device is
usually called a flip-flop.

Unfortunately the authors do not explain the construction of such
a device, though the 7474 and 74109 are real-world examples of it.

The idea of a FF that isn't partial to meta-stability is nice, but in
general not affordable within ASICs or FPGAs. That's why we have to be very
careful when signals cross clock boundaries.

The 7474 is a slightly tricky master-slave circuit.

The 7474 is not a master-slave flip-flop. It actually contains three
S-R flip-flops in a non-obvious configuration, very much unlike what
Paul Uiterlinden described.

I'm not familiar with the 7474, but I know that constructions with 3 latches
in sequence are sometimes used when transferring signals over a larger
distance. It creates, in some situations, a better clock data relation at
the receiving FF.

Regards,
Pieter Hulshoff

 

[Eric Smith]

Pieter Hulshoff <phulshof@xs4all.nl> writes:

Could we please all use the same terminology? A pulse (level) triggered
memory device is usually called a latch. An edge triggered memory device is
usually called a flip-flop.

The book I was quoting distinguishes between level-triggered (latch),
pulse-triggered (master-slave), and edge-triggered. Sorry, I don't know
what better terminology to use to describe it.

The point was that the behavior of a master-slave FF is NOT always
the same as that of an edge-triggered FF. This is why master-slave FFs
went out of style in the late 1970s.

The idea of a FF that isn't partial to meta-stability is nice, but in

That's not what they're talking about, and it's not even theoretically
possible to eliminate metastability.

The 7474 is not a master-slave flip-flop. It actually contains three
S-R flip-flops in a non-obvious configuration, very much unlike what
Paul Uiterlinden described.

I'm not familiar with the 7474, but I know that constructions with 3 latches
in sequence are sometimes used when transferring signals over a larger
distance. It creates, in some situations, a better clock data relation at
the receiving FF.

The 7474 does NOT have three in sequence. It has two SR flops in the
first stage, and one in the second. There's no easy way to explain it,
which is why I referenced the diagram in the TI data sheet.

 

[Ken Smith]

In article <4168e663$0$30036$e4fe514c@dreader13.news.xs4all.nl>,
Pieter Hulshoff <phulshof@xs4all.nl> wrote:
[...]

Could we please all use the same terminology? A pulse (level) triggered
memory device is usually called a latch. An edge triggered memory device is
usually called a flip-flop.

I'm using:

In the following, you can exchange "high" with "low" and get the neg.
polarity version.

The "D" input is the data input to the flip-flip

"edge-triggered" means that the output takes on the logic value that was
at the "D" input when the clock went from low to high and remains that way
until the next time the clock goes from low to high.


"pulse" "level triggered" and "latch" all refer to circuits where the
output either (a) follows the input or (b) is not useful while the clock
is high and holds the value when the clock is low. In most cases, the
output follows the input but the (b) case can also be true.

I'm not familiar with the 7474, but I know that constructions with 3 latches
in sequence are sometimes used when transferring signals over a larger
distance. It creates, in some situations, a better clock data relation at
the receiving FF.

The 3rd flip-flop in the "logic diagram" handles stearing of the PRE/ and
CLR/ signals it is in parallel with the main master/slave pair.

When dealing with signals coming in from the outside, it is common to put
a couple or 3 flip-flops in the path with a bit of logic around them.
These circuits, lower the odds of a glitch at the output at the cost of a
delay to the input signal. A M.S. state on the first stage has to remain
for a whole clock cycle to cause trouble. The odds of that are quite low.

--
--
kensmith@rahul.net forging knowledge