easy way for executing commands sequenced?

[poldi]

Hi all!

I am new to verilog and I have a little problem with it. I am using
Quartus WebII-Edition from Altera. My problem is: I dont know how to
execute commands sequenced inside an always@(trigger)-block. I've searched
the web but found only the #-operator. but this operator has no effect
according to the simulation runs.

example:

input nWRITE;
output dac_nWR;

wire dac_nWR;
reg dacr_nWR;

assign dac_nWR = dacr_nWR;

always@(posedge nWRITE) begin
#10 dacr_nWR = 1;
#10 dacr_nWR = 0;
end

I know of the possebility of using a finite state machine (FSM) for this
purpose but I am lazy and thougt there is another "smart" way of doing it.
In this example the compiler displays the warning: "dacr_nWR tied to GND"
which means he "thinks" there is no delay between these commands and
"optimizes" it to dacr_nWR=0 ...

So, is there a better way instead using FSMs?

sorry for the weird english and thank you in advance,
Martin.

 

[gabor]

Martin,

I'm not sure about Quartus, which may actually show you only a
post-translation RTL simulation, but a behavioral simulation should
in fact show dacr_nWR toggling high for 10 default periods (usually
1ns each) at the rising edge of nWRITE.

This does not change the fact that no synthesis tool will actually
create a working circuit from this code. Generally all delays are
ignored for synthesis. If your aim is to use this code in an FPGA
you need to create the appropriate state logic.

Have fun,
Gabor

poldi wrote:

Hi all!

I am new to verilog and I have a little problem with it. I am using
Quartus WebII-Edition from Altera. My problem is: I dont know how to
execute commands sequenced inside an always@(trigger)-block. I've searched
the web but found only the #-operator. but this operator has no effect
according to the simulation runs.

example:

input nWRITE;
output dac_nWR;

wire dac_nWR;
reg dacr_nWR;

assign dac_nWR = dacr_nWR;

always@(posedge nWRITE) begin
#10 dacr_nWR = 1;
#10 dacr_nWR = 0;
end

I know of the possebility of using a finite state machine (FSM) for this
purpose but I am lazy and thougt there is another "smart" way of doing it.
In this example the compiler displays the warning: "dacr_nWR tied to GND"
which means he "thinks" there is no delay between these commands and
"optimizes" it to dacr_nWR=0 ...

So, is there a better way instead using FSMs?

sorry for the weird english and thank you in advance,
Martin.

 

[poldi]

Generally all delays are
ignored for synthesis. If your aim is to use this code in an FPGA
you need to create the appropriate state logic.

That was the hunch i had but i haven't found any book or web page which
says it in this clear way.
thank you for your answer, Gabor.

Martin.