dynamically enable/disable timing checks?

[unfrostedpoptart]

Hi all.

I can't see how to do this, so I'm asking. I have some parts of my
design that will generate setup time violations during the
initialization phase of the test. This is a back-annotated netlist
simulation. I know how to turn off timing checks on a particular
register, but that's for the whole simulation. I want to turn off the
timing check at the beginning of the simulation, but then enable it at
a particular time. Can this be done?

Thanks,

David

 

[Rajkumar Kadam]

On May 24, 11:18 pm, unfrostedpoptart <d...@therogoffs.com> wrote:

Hi all.

I can't see how to do this, so I'm asking. I have some parts of my
design that will generate setup time violations during the
initialization phase of the test. This is a back-annotated netlist
simulation. I know how to turn off timing checks on a particular
register, but that's for the whole simulation. I want to turn off the
timing check at the beginning of the simulation, but then enable it at
a particular time. Can this be done?

Thanks,

David

Hi David!
(I)
If the setup violation should not affect your real design, then the
timing
violation should not affect your backannotated simulation also.
One of the ways you do this is to gate the output of the so called
register
during the INIT state, so that the violation does not affect your
simulation.
(II)
Supposing that the violation messages is your only problem rather than
simulation, then
in that case just force the input/output of the register to some fixed
value and release
it when you want it to.
Hope this helps

Rajkumar...

 

unfrostedpoptart wrote:

Hi all.

I can't see how to do this, so I'm asking. I have some parts of my
design that will generate setup time violations during the
initialization phase of the test. This is a back-annotated netlist
simulation. I know how to turn off timing checks on a particular
register, but that's for the whole simulation. I want to turn off the
timing check at the beginning of the simulation, but then enable it at
a particular time. Can this be done?

Depends on whether your simulator supports the $disable_warnings
and $enable_warnings system tasks. These were not standardized,
but come from Verilog-XL, so many simulators will support them.

 

[Alex]

On May 24, 2:18 pm, unfrostedpoptart <d...@therogoffs.com> wrote:

Hi all.

I can't see how to do this, so I'm asking. I have some parts of my
design that will generate setup time violations during the
initialization phase of the test. This is a back-annotated netlist
simulation. I know how to turn off timing checks on a particular
register, but that's for the whole simulation. I want to turn off the
timing check at the beginning of the simulation, but then enable it at
a particular time. Can this be done?

Thanks,

David

Usually, timing checks are enabled when internal-to-module "notifier"
register is high. It is possible to control the value of notifier
register from the outside during simulation run.

-Alex

 

[unfrostedpoptart]

Thanks for the various suggestions. I'm using NC and VCS. I'll have
to look at our code and our libraries and see which ideas would work
best.

David

 

[Ajeetha (www.noveldv.com)]

On May 28, 10:14 am, unfrostedpoptart <d...@therogoffs.com> wrote:

Thanks for the various suggestions. I'm using NC and VCS. I'll have
to look at our code and our libraries and see which ideas would work
best.

David

David,
I would also recommend the $disable_warning/$enable_warning as
Steve suggested. There are also TCL commands such as "tcheck" that let
you do similar things, AFAIK MTI and VCS support them. Not sure of NC.
The good thing about TCL is, no need to recompile, flip side is you
*may* loose some performance at run time. So depending on which one is
more you choose the correct one for you.

Regards
Ajeetha, CVC
www.noveldv.com

 

unfrostedpoptart wrote:

Thanks for the various suggestions. I'm using NC and VCS. I'll have
to look at our code and our libraries and see which ideas would work
best.

I am pretty sure that NC supports $disable_warnings for this.

 

[D. Roberts]

On Wed, 06 Jun 2007 12:41:24 -0700, sharp wrote:

unfrostedpoptart wrote:
Thanks for the various suggestions. I'm using NC and VCS. I'll have
to look at our code and our libraries and see which ideas would work
best.

I am pretty sure that NC supports $disable_warnings for this.

From TCL with ncsim you can use the command

tcheck [-on|-off] <hierarchy path>

from the ncsim prompt type: tcheck -help

--David