Dynamic Voltage switching for FPGA IO

K

kolar

Guest
Hi,

For my project we are using Xilinx Virtex-6 FPGAs. I have a specifi
requirement where I would like to change the IO voltage(VCCO) of one ban
from 3.3V to 1.8V. Assuming that the core is working at a different voltag
and IOs on different. Core at the start works with 3.3V and then drives th
IOs to Z and then we would like to change the VCCO of this particular ban
and start working at 1.8V.

Note that we do not want to recreate bitmap or reload the design. Whil
this swithcing is happening we would like to let our core work continuousl
with other set of IO bank whose voltage is not switching.

Is this dynamic voltage switching possible. If yes it would be great t
know how this can be achieved. I believe some kind of registers will nee
to be programmed to achieve this.

Thanks
Kolar



---------------------------------------
Posted through http://www.FPGARelated.com
 
I would of thought that if it was possible to do that then the user guide
would tell you how. Cant you just use an external circuit to do the sam
thing?

Jon

---------------------------------------
Posted through http://www.FPGARelated.com
 
Hi,

For my project we are using Xilinx Virtex-6 FPGAs. I have a specific
requirement where I would like to change the IO voltage(VCCO) of one bank
from 3.3V to 1.8V. Assuming that the core is working at a differen
voltage
and IOs on different. Core at the start works with 3.3V and then drive
the
IOs to Z and then we would like to change the VCCO of this particula
bank
and start working at 1.8V.

Note that we do not want to recreate bitmap or reload the design. While
this swithcing is happening we would like to let our core wor
continuously
with other set of IO bank whose voltage is not switching.

Is this dynamic voltage switching possible. If yes it would be great to
know how this can be achieved. I believe some kind of registers will need
to be programmed to achieve this.

Thanks
Kolar
Click to expand...
I am > 90% certain that it isn't possible.
But just to be sure, ask at:
http://forums.xilinx.com/t5/Virtex-Family-FPGAs/bd-p/Virtex


---------------------------------------
Posted through http://www.FPGARelated.com
 
On Feb 3, 5:24 am, "kolar" <kamleshrr@n_o_s_p_a_m.gmail.com> wrote:
Hi,

For my project we are using Xilinx Virtex-6 FPGAs. I have a specific
requirement where I would like to change the IO voltage(VCCO) of one bank
from 3.3V to 1.8V. Assuming that the core is working at a different voltage
and IOs on different. Core at the start works with 3.3V and then drives the
IOs to Z and then we would like to change the VCCO of this particular bank
and start working at 1.8V.

Note that we do not want to recreate bitmap or reload the design. While
this swithcing is happening we would like to let our core work continuously
with other set of IO bank whose voltage is not switching.

Is this dynamic voltage switching possible. If yes it would be great to
know how this can be achieved. I believe some kind of registers will need
to be programmed to achieve this.

Thanks
Kolar

---------------------------------------        
Posted throughhttp://www.FPGARelated.com
Click to expand...
The IO configuration bits would need to be reprogrammed to enable this
to work. This isn't a register write, but a reload of the
configuration bits.

Ed McGettigan
--
Xilinx Inc.
 
On Feb 3, 8:24 am, "kolar" <kamleshrr@n_o_s_p_a_m.gmail.com> wrote:
Hi,

For my project we are using Xilinx Virtex-6 FPGAs. I have a specific
requirement where I would like to change the IO voltage(VCCO) of one bank
from 3.3V to 1.8V. Assuming that the core is working at a different voltage
and IOs on different. Core at the start works with 3.3V and then drives the
IOs to Z and then we would like to change the VCCO of this particular bank
and start working at 1.8V.

Note that we do not want to recreate bitmap or reload the design. While
this swithcing is happening we would like to let our core work continuously
with other set of IO bank whose voltage is not switching.

Is this dynamic voltage switching possible. If yes it would be great to
know how this can be achieved. I believe some kind of registers will need
to be programmed to achieve this.

Thanks
Kolar

---------------------------------------        
Posted throughhttp://www.FPGARelated.com
Click to expand...
I'm pretty sure the maximum Vcco for Virtex 6 is 2.5V, not 3.3V.
Within the
usable range of Vcco, you can use the same LVCMOS I/O standard without
changing the bitstream, just by picking the lowest voltage to be
used. What
you end up with is I/O that drives considerably stronger that the
standard
you picked when Vcco is larger than that standard's nominal value.
For
example starting with LVCMOS_18 @4 mA and driving Vcco to 2.5V
will result in much more drive than 4 mA. If you really need to
change
IO standard, rather than "fudging it" with variable Vcco LVCMOS,
then you would need to do at least partial reconfiguration.

-- Gabor
 
Gabor <gabor@alacron.com> wrote:

On Feb 3, 8:24=A0am, "kolar" <kamleshrr@n_o_s_p_a_m.gmail.com> wrote:
Hi,

For my project we are using Xilinx Virtex-6 FPGAs. I have a specific
requirement where I would like to change the IO voltage(VCCO) of one bank
from 3.3V to 1.8V. Assuming that the core is working at a different volta=
ge
and IOs on different. Core at the start works with 3.3V and then drives t=
he
IOs to Z and then we would like to change the VCCO of this particular ban=
k
and start working at 1.8V.

Note that we do not want to recreate bitmap or reload the design. While
this swithcing is happening we would like to let our core work continuous=
ly
with other set of IO bank whose voltage is not switching.

Is this dynamic voltage switching possible. If yes it would be great to
know how this can be achieved. I believe some kind of registers will need
to be programmed to achieve this.

Thanks
Kolar

--------------------------------------- =A0 =A0 =A0 =A0
Posted throughhttp://www.FPGARelated.com

I'm pretty sure the maximum Vcco for Virtex 6 is 2.5V, not 3.3V.
Within the
usable range of Vcco, you can use the same LVCMOS I/O standard without
changing the bitstream, just by picking the lowest voltage to be
used. What
you end up with is I/O that drives considerably stronger that the
standard
you picked when Vcco is larger than that standard's nominal value.
For
example starting with LVCMOS_18 @4 mA and driving Vcco to 2.5V
will result in much more drive than 4 mA. If you really need to
change
IO standard, rather than "fudging it" with variable Vcco LVCMOS,
then you would need to do at least partial reconfiguration.
Click to expand...
In addition: I recall someone already tried something similar and the
conclusion was that you don't need reconfiguration.

I'd just test it on a prototype but I'm quite sure it will just work
OK. What you need to think of is that the outputs of the Xilinx FPGA
are adjustable current sinks/sources. Like Gabor says the current can
be adjusted by the bitstream and ofcourse the current will vary with
supply voltage. There is nothing magical about it.

--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
nico@nctdevpuntnl (punt=.)
--------------------------------------------------------------
 
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