R
Ronit Edri
Guest
Hi
I defined an interface in system verilog and added a wire which I
assigned to it RTL signals.
In the sv testbench, I force it in a loop, I do HOT ONE to the wire
which is 48 bits size.
when I run the test I get the following error:
Error-[DTIDCIL] Dynamic type in declarative context
/home/redri/msp5_dv/direct/msp/tests/gpio_in.sv, 23
"force msp5_env_top.u_gpio_in_if.gpio = (1 << i);"
Argument: i
Automatic variable may not be used in declarative context.
the wire is the "gpio"
thanks for any help
I defined an interface in system verilog and added a wire which I
assigned to it RTL signals.
In the sv testbench, I force it in a loop, I do HOT ONE to the wire
which is 48 bits size.
when I run the test I get the following error:
Error-[DTIDCIL] Dynamic type in declarative context
/home/redri/msp5_dv/direct/msp/tests/gpio_in.sv, 23
"force msp5_env_top.u_gpio_in_if.gpio = (1 << i);"
Argument: i
Automatic variable may not be used in declarative context.
the wire is the "gpio"
thanks for any help