Dynamic Array in VHDL

[live4perfection]

want to use dynamic range of array , so using "N" for converting a
incoming vector signal to integer. Using the specifc incoming port "Size
gives me an error, while fixed vector produces perfect output.


architecture EXAMPLE of Computation is

signal size :std_logic_vector (7 downto 0);

process (ACLK, SLAVE_ARESETN) is

variable N: integer:=conv_integer ("00000111") ; ---WORKING

--variable N: integer:=conv_integer (size) ; -- Not working
type memory is array (N downto 0 ) of std_logic_vector (31 downto
);

variable RAM :memory;


Only reason to do this type of coding is send as much data as possible t
FPGA .As I need to send Data from DDR to Custom IP via DMA in vivado ma
be more than 100 MB. so kindly guide me if I am trying to implement i
wrong way as stated above.

I am thinking to make a counter to address ram, and have it reset whe
it's greater than size but confused how to do it . Can anyone provide m
some example.

Thanks


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[glen herrmannsfeldt]

live4perfection <106037@fpgarelated> wrote:

want to use dynamic range of array , so using "N" for converting an
incoming vector signal to integer. Using the specifc incoming port "Size"
gives me an error, while fixed vector produces perfect output.

Remember, VHDL describes hardware. Though it can also be used for
test benches and simulation. In hardware, you have to know
how big things are.

architecture EXAMPLE of Computation is

signal size :std_logic_vector (7 downto 0);

process (ACLK, SLAVE_ARESETN) is

variable N: integer:=conv_integer ("00000111") ; ---WORKING

--variable N: integer:=conv_integer (size) ; -- Not working
type memory is array (N downto 0 ) of std_logic_vector (31 downto 0
);
variable RAM :memory;

When you buy RAM chips from the store, you have to say how many
bits you want. That can't be a variable.

Only reason to do this type of coding is send as much data as possible to
FPGA .As I need to send Data from DDR to Custom IP via DMA in vivado may
be more than 100 MB. so kindly guide me if I am trying to implement in
wrong way as stated above.

That might mean an interface to an external DRAM. You write the
inteface, not the DRAM.

I am thinking to make a counter to address ram, and have it reset when
it's greater than size but confused how to do it . Can anyone provide me
some example.

-- glen

 

You didn't mention whether this is purely for simulation (e.g for architecture exploration) or for synthesis (building and FPGA).

I am not sure that referencing a variable for a type declaration is correct, but some synthesis tools may allow it anyway (since the variable could not have changed value except at run time.)

Declarations must be based on static information, known at compile time.

Your entity could use a generic (a static kind of "port") to pass this size information in at compile/synthesis time, but that is about as dynamic as it gets for architecture or process declarative regions.

Most tools allow specifying the value of top level generics on the command line and/or in a project file.

For simulation, subprograms can declare items based on argument values, but for synthesis, this places constraints on how the subprogram is called, and whether those argument values can be known at synthesis time.

VHDL (for simulation only) has dynamic memory allocation, and pointers (called access types) with which you can dynamically create data structures. But they are not synthesizable.

Andy