DVI-decoder clock question

[Mawa_fugo]

Let say I have two DVI streams - generated by two encoders, those have
different video contents but same pixel clock

The two tmds streams travel thru cables then - are decoded by two
decoders - then fed into an FPGA

The question is how the two clocks at the output of the encoders look
like, are they the same? Can we use only one clock for both channel to
clock the data in the FPGA?

========

My theory is that, the original clock goes to two 10x then divided
back 1/10, so they are supposedly be in same phase... or what
else ???

 

[johnp]

On Jul 29, 6:59 am, Mawa_fugo <cco...@netscape.net> wrote:

Let say I have two DVI streams - generated by two encoders, those have
different video contents but same pixel clock

The two tmds streams travel thru cables then - are decoded by two
decoders - then fed into an FPGA

The question is how the two clocks at the output of the encoders look
like, are they the same? Can we use only one clock for both channel to
clock the data in the FPGA?

=======
My theory is that, the original clock goes to two 10x then divided
back 1/10, so they are supposedly be in same phase... or what
else ???

Although you may make it work in the lab, I doubt that you can
robustly use
only one clock. If the encoders are using different crystals, their
frequencies
will be slightly off and will drift over time. This will break
things. Also, each
of the encoders may change their phase relationships as they warm up.

If you're running at high clock rates, you're headed for a lot of
heart-burn.

John P

 

[Ed McGettigan]

On Jul 29, 6:59 am, Mawa_fugo <cco...@netscape.net> wrote:

Let say I have two DVI streams - generated by two encoders, those have
different video contents but same pixel clock

The two tmds streams travel thru cables then - are decoded by two
decoders - then fed into an FPGA

The question is how the two clocks at the output of the encoders look
like, are they the same? Can we use only one clock for both channel to
clock the data in the FPGA?

=======
My theory is that, the original clock goes to two 10x then divided
back 1/10, so they are supposedly be in same phase... or what
else ???

If the same source is used for the pixel clock of both encoders, and
by same I mean only one physical clock oscillator is used for both
encoders, then you can be sure that that the bit rate for both
encoders is the same. However, there will be no guaranteed phase
relationship between the data output of the two encoders.

You could use the same original clock source, or one of the two clock
outputs from the encoders, and a dynamic phase aligner for the
receivers in the FPGA to cut down on the clocking resource requirement
in the FPGA. However, you may find it easier to use the clock/data
from each encoder to capture the data and then put it through a simple
shallow depth synchronous FIFO and use a single global clock for the
rest of your system.

Ed McGettigan
--
Xilinx Inc.

 

[Mawa_fugo]

On Aug 4, 12:51 pm, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote:

On Jul 29, 6:59 am, Mawa_fugo <cco...@netscape.net> wrote:

Let say I have two DVI streams - generated by two encoders, those have
different video contents but same pixel clock

The two tmds streams travel thru cables then - are decoded by two
decoders - then fed into an FPGA

The question is how the two clocks at the output of the encoders look
like, are they the same? Can we use only one clock for both channel to
clock the data in the FPGA?

=======
My theory is that, the original clock goes to two 10x then divided
back 1/10, so they are supposedly be in same phase... or what
else ???

If the same source is used for the pixel clock of both encoders, and
by same I mean only one physical clock oscillator is used for both
encoders, then you can be sure that that the bit rate for both
encoders is the same.  However, there will be no guaranteed phase
relationship between the data output of the two encoders.

You could use the same original clock source, or one of the two clock
outputs from the encoders, and a dynamic phase aligner for the
receivers in the FPGA to cut down on the clocking resource requirement
in the FPGA.  However, you may find it easier to use the clock/data
from each encoder to capture the data and then put it through a simple
shallow depth synchronous FIFO and use a single global clock for the
rest of your system.

Ed McGettigan
--
Xilinx Inc.

Good idea, that's what I'm heading to - thanks all for advices