R
Roger Light
Guest
Hi,
I'm fairly new to synthesis tools and vhdl as well. I am trying to
synthesise a fairly simple design using PKS but am running into problems.
The top cell is just a structural declaration of an array of a different
cell:
entity Top is
Port ( ... );
end Top;
architecture struct of Top is
component child
Port ( ... );
end component;
begin
c: for i in 0 to 63 generate
BlockWithDeclarativePart:block
for cx : child use entity work.child(struct);
begin
cx : child
port map ( ... );
end block;
end generate;
end struct;
The child block contains further structural and behavioural blocks.
Now in PKS (from SPR50) I load all of the VHDL and associated files,
then run build generic, add some constraints and then run optimise. This
is where my "problem" shows itself - I get lots of info lines stating
for example:
Info: Duplicated module 'child' as 'child_1' and bound to instance
'cx_1' in module 'Top' <FNP-700>.
This info line is given for every single port map line in every instance
(so cx_1 is treated as seperate to cx_2 and the cells are duplicated
again and so on down the hierarchy) as far as I can tell and so I end up
with a synthesised verilog file that is around 120,000 lines long from
just 10 small vhdl input files. This equates to around 5000 cells, the
vast majority of which are essentially identical.
Is there any way I can make the synthesis work a little more
intelligently, or is this just the way it is? Importing and using 5000
cells in dfII is kind of unwieldy...
Thanks,
Roger
I'm fairly new to synthesis tools and vhdl as well. I am trying to
synthesise a fairly simple design using PKS but am running into problems.
The top cell is just a structural declaration of an array of a different
cell:
entity Top is
Port ( ... );
end Top;
architecture struct of Top is
component child
Port ( ... );
end component;
begin
c: for i in 0 to 63 generate
BlockWithDeclarativePart:block
for cx : child use entity work.child(struct);
begin
cx : child
port map ( ... );
end block;
end generate;
end struct;
The child block contains further structural and behavioural blocks.
Now in PKS (from SPR50) I load all of the VHDL and associated files,
then run build generic, add some constraints and then run optimise. This
is where my "problem" shows itself - I get lots of info lines stating
for example:
Info: Duplicated module 'child' as 'child_1' and bound to instance
'cx_1' in module 'Top' <FNP-700>.
This info line is given for every single port map line in every instance
(so cx_1 is treated as seperate to cx_2 and the cells are duplicated
again and so on down the hierarchy) as far as I can tell and so I end up
with a synthesised verilog file that is around 120,000 lines long from
just 10 small vhdl input files. This equates to around 5000 cells, the
vast majority of which are essentially identical.
Is there any way I can make the synthesis work a little more
intelligently, or is this just the way it is? Importing and using 5000
cells in dfII is kind of unwieldy...
Thanks,
Roger