S
Swamy Muddu
Guest
Hi,
I am trying to do gate-level dual Vt assigment using PKS. I have two
timing libraries corresponding to the low-leakage (High-VT) and
high-performance (Low-VT). I read both these timing libraries into PKS
and enable dual-Vt assignment mode. Ideally, the tool is supposed to
replace cells on all "non-critial" (==> slack +ve) paths to high-VT
cells. On timing-critical paths, the tool should insert leaky, but fast
cells.
However, the tool is inserting high-VT cells only. There is no single
low-VT cell in the design after synthesis. To force the tool to use
low-VT cells, I tightened my timing constraints and prioritized area
but the problem is still there.
If you have run gate-level dual-Vth assignment in PKS before, did you
come across these kinds of problems? Any pointers to webpages / docs
would be useful.
Thanks,
S Muddu
I am trying to do gate-level dual Vt assigment using PKS. I have two
timing libraries corresponding to the low-leakage (High-VT) and
high-performance (Low-VT). I read both these timing libraries into PKS
and enable dual-Vt assignment mode. Ideally, the tool is supposed to
replace cells on all "non-critial" (==> slack +ve) paths to high-VT
cells. On timing-critical paths, the tool should insert leaky, but fast
cells.
However, the tool is inserting high-VT cells only. There is no single
low-VT cell in the design after synthesis. To force the tool to use
low-VT cells, I tightened my timing constraints and prioritized area
but the problem is still there.
If you have run gate-level dual-Vth assignment in PKS before, did you
come across these kinds of problems? Any pointers to webpages / docs
would be useful.
Thanks,
S Muddu